VLSI, VHDL, Verilog Interview Questions

1. Give the full term of VHDL.

1. Very High Definition Language
2. Very High Speed Integration Hardware Description Language
3. Very High Description Language
4. Very High Speed Scaling Hardware Describing Language

Ans: 2) Very High Speed Integration Hardware Description Language

For basic VHDL Tutorials, Click Here!

2. What is the number of Metal Oxide Filed Effect Transistors are needed to construct a Bi-complementary metal Oxide Semiconductor NOR gate which have two input?

1. 5 MOSFETs
2. 6 MOSFETs
3. 7 MOSFETs
4. 8 MOSFETs

Ans: 3) 7 MOSFETs

“How a Logic gate is designed in VLSI?” Find the answer here!

3. What is the effect of ‘Delay’ if the power supply voltage gets increased?

1. Increases
2. Decreases
3. Remains the same
4. Delay has nothing o do with power supply.

Ans: 2) Decreases

4. Which is true about VLSI design?

1. VLSI is a sequential process which has feedback loops.
2. VLSI is a parallel process which has no feedback loops.
3. VLSI is both sequential and parallel process that has feedback loops.
4. VLSI is a sequential process which has no feedback loops.

Ans: 3) VLSI is both sequential and parallel process that has feedback loops.

For more details about Verilog Interview Questions and other topic like VLSI Design, Check this!

5. What is the use of CAD tools in VLSI design?

1. It automates the VLSI design.
2. It reduces the design cycle time.
3. It reduces the chance of errors.
4. All of the above.

Ans: 4) All of the above.

6. Which type of product is more suitable for FPGA based Design?

1. Large scale product development.
2. High Speed applications.
3. Prototype development.
4. Low power applications.

Ans: 3) Prototype development.

What is Verilog? What is system Verilog? and other Verilog Interview Questions and Answers are here!

7. What is the relation between interconnect delay and gate delay?

1. The Relation is technology dependent.
2. Gate delay always more than interconnect delay.
3. Interconnect delay always more than the gate delay.
4. They are same.

Ans: 1) The relation is technology dependent.

8. State True or False

Statement: For a Y chart, the details of design information increases when moved from the centre to the periphery.

1. True
2. False

Ans: (2). False

9. Why a short channel device is preferred?

1. It is easier for fabrication.
2. It has lower power consumption.
3. It has high speed.
4. It has better output characteristics.

Ans: 3) It has high speed.

10. Where does the subthreshold operation of MOSFET find applications?

1. Memories.
2. Charge coupled devices.
3. Biomedical applications.
4. None of the above.

Ans: 3) Biomedical applications.

11. What is the relation between the ON-resistance of MOSFET and gate to source voltage (Vgs)?

1. ON-resistance linearly increases with Vgs.
2. ON-resistance linearly decreases with Vgs.
3. ON-resistance exponentially increases with Vgs.
4. ON-resistance non-linearly decreases with Vgs.

Ans: 4) ON-resistance non-linearly decreases with Vgs.

12. What is the threshold voltage of an EMOSFET?

1. Equal to 0 V.
2. Less than 0 V.
3. Greater than 0 V.
4. None of the above.

Ans: 3) Greater than 0 V.

13. Find the odd one out.

1. Channel length modulation
2. Subthreshold Conduction
3. Hot carrier effect.
4. Body Effect

Ans: 4) Body effect. (All the other options are 2^nd order effect).

14. How does doping density change for constant voltage scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 2) Increases by a factor of s2.

15. How does power dissipation occur for full scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 3) Decreases by a factor of s2.

16. How does power dissipation occur for constant voltage scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 1) Increases by a factor of s.

17. What is the main advantage of depletion load NMOSFET inverter over EMOSFET load?

1. Less power dissipation
2. Easier fabrication process
3. Sharper Vtc transitions and better noise margins.
4. None of the above.

Ans: 3) Sharper Vtc transitions and better noise margin.

18. Why is polysilicon used for the gate in MOSFET?

1. Because it is a semi-metal.
2. Because it has lattice matching with Silicone
3. Because it is easier to fabricate.
4. None of the above.

Ans: 2) Because it has lattice matching with silicone.

19. State True or False

Statement: In full scaling, the magnitude of the electric field is constant.

1. True
2. False

Solution: (1). True

20. Which of the given statement is true regarding a MOSFET inverter?

1. One PMOSFET and one resistor are needed to implement a MOSFET inverter.
2. One NMOSFET and one resistor are needed to implement a MOSFET inverter.
3. Two PMOSFETs.
4. Two NMOSFETs.

Ans: 2) One NMOSFET and one resistor is needed to implement a MOSFET inverter.

21. On which factors, the power dissipation of a CMOS inverter depends?

1. Supplied Voltage.
2. NMOSFET’s channel width.
3. PMOSFET’s channel width.
4. All of the above.

Ans: 1) Supplied Voltage

22. State True or False

Statement: The PMOS transistors act as Pull-up network in a CMOS inverter.

1. True
2. False

Solution: (1). True

23. Which of the following effect has no contribution to deviate the ideal situation of a current mirror circuit?

1. DIBL effects.
2. Threshold offset between two transistors
3. Channel length modulation
4. Imperfect geometrical matching.

Ans: 1) DIBL effects.

24. What does the ASIC cell library contain?

1. The physical layout of the cells
2. Routing model of the cells
3. Timing model of the cells
4. All of the above.

Ans: 1) Physical layout of the cells.

25. Why does lowest propagation delay occur through a gate?

1. Due to – strong transistor, high temperature, high voltage.
2. Due to – strong transistor, low temperature, high voltage.
3. Due to – Weak transistor, high temperature, high voltage.
4. Due to – weak transistor, low temperature, low voltage.

Ans: 3) Due to – Weak transistor, high temperature, high voltage.

26. Which of the following is true about VLSI logic design?

1. VLSI minimizes the area and delay
2. VLSI minimizes the area at the cost of delay
3. VLSI maximizes speed by decreasing area
4. VLSI minimizes delay by reducing the area

Ans: 2) VLSI minimizes the area at the cost of delay.

27. What is a hard macro?

1. Flexible Block
2. Fixed Block
3. Flexible block with a fixed aspect ratio
4. Flexible block with a flexible aspect ratio

Ans: 2) Fixed Block

28. State True or False

Statement: The full form of SPICE is – Simulation Program with Integrated Circuit Emphasis.

1. True
2. False

Solution: (1). True

29. What is the equivalent circuit for CMOS comparator?

1. Uncompensated CMOS OPAMP.
2. Compensated CMOS OPAMP.
3. Partially Compensated CMOS OPAMP.
4. None of the above is true.

Ans: 1) Uncompensated CMOS OPAMP.

30. What is the relation between the equivalent resistance of a switched capacitor and the clock frequency?

1. The resistance is proportional to clock frequency.
2. The resistance is inversely proportional to clock frequency.
3. The resistance is proportional to the square of the clock frequency.
4. The resistance is inversely proportional to the square of the clock frequency.

Ans: 2) The resistance is inversely proportional to clock frequency.

31. What is the relation between the equivalent resistance of a switched capacitor and the capacitance?

1. The resistance is proportional to the capacitance.
2. The resistance is inversely proportional to the capacitance.
3. The resistance is proportional to the square of the capacitance.
4. The resistance is inversely proportional to the square of the capacitance.

Ans: 2) The resistance is inversely proportional to the capacitance.

32. What is the condition for domination by Diffusion Current?

1. Strong Inversion
2. Weak Inversion
3. Both Strong and weak inversion.
4. Cannot be determined.

Ans: 2) Weak Inversion.

33. What is the condition for domination by Drift Current?

1. Strong Inversion
2. Weak Inversion
3. Both Strong and weak inversion.
4. Cannot be determined.

Ans: 1) Strong Inversion.

34. State True or False

Statement: In the cascode current mirror, the output resistance is increased.

1. True
2. False

Solution: (1). True

35. State True or False

Statement: A current mirror circuit can be used as a current amplifier by increasing the (W/L) ratios of the mirrored and source MOSFET

1. True
2. False

Solution: (1). True

36. Which connections of NMOS in PDN, help to realize the AND terms?

1. Cascade Connection
2. Anti – parallel Connections
3. Series Connections
4. Parallel Connections

Ans: 3) Series Connections

37. Which type of transistor can pass logic-high value perfectly, but not the logic-low value?

1. NMOSFET
2. PMOSFET
3. CMOS
4. None of the above

Ans: 2) PMOSFET

38. What is the minimum number of transistors needed to design an XOR gate?

1. Three
2. Four
3. Five
4. Six

Ans: 4) Six

39. Which type of logic design provides the minimum propagation delay?

1. Emitter Coupled Logic
2. Transistor Transistor Logic
3. Register Transistor Logic
4. Diode Transistor Logic

Ans: 1) Emitter Coupled Logic

40. State True or False

Statement: Dynamic CMOS logic operates using two non-overlapping clock pulses.

1. True
2. False

Solution: (2). False.

For more VLSI related topic and Verilog interview questions click here

Topics for Discussion

A. Xilinx

B. Prerequisites for Verilog HDL Using Xilinx

C. Xilinx Installation process

D. Creating your first Verilog project with XILINX

XILINX

Xilinx is a USA based tech-company which provides programmable logic devices. We will use Xilinx’s software “ISE 14.7 Simulator to implement Verilog designs. Xilinx is also used for VHDL implementations. Though some of the coding structure of Verilog is same as VHDL, there are fundamental differences between them.

First of all learn Verilog! Click Here!

Prerequisites for Verilog using Xilinx

Before getting started with Verilog with Xilinx, there are some prerequisites for an user. They are listed below.

• Must have some knowledge of digital electronics. At least bits of knowledge of basic logic gates and sequential circuits are required.
• An uninterrupted internet connection is a must.
• A healthy amount of free memory is required to run the software smoothly. At least 20 GB space is needed in your machine.
• Create an account on Xilinx’s website with an accessible email-id. The license will be mailed in that email-id.
• We are demonstrating this tutorial for windows only.   

What is VHDL? What is the difference between Verilog & VHDL?

Xilinx Installation Process

• Step 1: Download the software from the internet. The link to download Xilinx is given below –

(It is a 6GB ZIP file, ensure internet connection and space) The link for windows –

https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_ISE_DS_Win_14.7_1015_1.tar

There are other downloadable options available. You can choose according to your requirement and choice from the below given link.

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html

• Step 2: Unzip the file. To unzip the file, right-click on the file, and there will be an option to extract all. After the extraction, the file name should be – ‘Xilinx_ISE_DS_Win_14.7_1015.1”.

Point to be noted – Both the download and extraction will need a lot of time depending upon internet speed and storage availability. The installation will require a lot of time too. So, don’t panic, be patient.

• Step 3: Open the extracted file. There is a file named – ‘xsetup’. Double click on that file. It will start the installation.

1. There will be another pop-up, choose the ‘ISE WebPACK’ option to continue.

It will start the final installation process.

• Step 4: After the software gets installed in your PC, some tasks must be performed. Do these tasks carefully. Also, update the license from Xilinx. Those steps are given in the previous article; please check it out before we start with our first Verilog Project. The link is given below.

https://lambdageeks.com/vhdl-process-xilinx-guide/

Creating your first Verilog project with XILINX

We will first implement a simple AND gate model using XILINX. The logical representation of AND gate is Y = AB; A and B are the two inputs, while Y is the output. The truth table is given below.

A	B	Y =AB
0	0	0
0	1	0
1	0	0
1	1	1

• Step 1: Open the project navigator by double clicking the icon on the desktop.
• Step 2: Go to ‘File’ and then ‘New Project’. File -> New Project

• Step 3: Type a name for your project and select the storage location. It is advised not to use basic logic gate names as they are reversed keywords. Also, don’t forget to copy the name of your project; it will help your letter. Click on the ‘Next’ button to proceed.

• Step 4: Now, you have to set up a few things. Be careful while setting up all these things. Any mistake will lead to failure in the long-term result.

• Property Name: Value
• Evaluation Development Board: None Specified
• Product Category: All
• Family: Spartan3
• Device: XC3S50
• Package: PQ208
• Speed: -4
• Top Source Type: HDL
• Synthesis Tool: XST (VHDL/Verilog)
• Simulator: lSim (VHDL/Verilog)
• Preferred Language: Verilog
• Property Specification in Project File: Store all values
• Manual Compile Order: Leave the checkbox, don’t click on it.
• VHDL Source Analysis Standard: VHDL-93
• Enable Message Filtering:  Leave the checkbox, don’t click on it.

Click on ‘Next’ to proceed.

• Step 5: Now, click on ‘Finish; for the next pop-up.

• Step 6: A new window will be opened up in the ISE simulator. Inside the design tab at the left corner, and under the Hierarchy bar, the model will have appeared. Move your cursor on the folder just below the named model.

Then right-click on the folder (in our case the name of the folder is – ‘xc3s50-4pq208’). Then, select the new source.

• Step 7: In the new window, choose the ‘Verilog Module’ and paste the same name you have copied in the step 3. You can also get that name from the location tab. Click on ‘Next’ to proceed.

• Step 8: The defining module will come up. But we will not define the ports now. Just click on ‘Next’.

• Step 9: Click on “Finish” for the next window pop-up.

• Step 10: A code editor will be opened up.
  • Now change the project name written in the editor to “AND”. For our case, we change it from ‘LAMBDAGEEKS_VERILOG_AND_GATE’ to ‘AND’.

• Now write down the port declarations as follow.

module AND (

                        input I1, I2,

                        output O

                        );

endmodule

• Now assign the AND gate in-between the input and output.

assign O = I1 & I2;

• Save the code.
• Step 11: Now, on the left side of the window, under the design bar, you can see a tab named “Process AND”.
  • Expand the ‘Synthesis – XST’ from there.
  • Double click on the ‘Check Syntax’. It will show a green tick, denoting success.

• Step 12: Now again go back to the top-left section. Right-click  on the ‘xc3s50-4pq208’ file. Choose a new source from there.

• Step 13: Choose Verilog Module from the given list. Then put a file name. We put “LAMBDAGEEKS_TOP_MODULE” as the name. Click on the ‘Next’ to proceed.

1. A pop-up named ‘Define Module’ will come. Do not define anything here. Click on the ‘Next’.

• Click on ‘Finish’ for the next popped-up window.

• Step 14: A code editor will be opened up. You can erase all the comment section from the code editor.
  • Now, check the Hierarchy Section at the top left. Right-click on the Module Name given by you. For our case, it is – ‘LAMBDAGEEKS_TOP_MODULE’.
  • Some options will come upon the right click. Choose the option – ‘Set as Top Module’.

• A window will pop-up. Click on ‘YES’ to continue.

• Step 15: Now, we have to write some code using the code editor. It describes the input and output with the gate implementation. The following code is written for AND gate –

module LAMBDAGEEKS_TOP_MODULE(

            input I1, I2,

            output O

  );

            AND and1(I1,I2,O);

endmodule

• Step 16:  Now go to the left down part at ‘Process: LAMBDAGEEKS_TOP_MODULE’ section.
  • Now Expand the ‘Synthesis -XST’ part.
  • Double click on the ‘Check Syntax’. It will show a green tick denoting success after a few seconds.
  • Then, Double click on the ‘Synthesis – XST’ option. It will take a few seconds to show a green tick.

• Step 17:  View for RTL Schematic.
  • Double click on the ‘View RTL Schematic’ option.
  • A window named – ‘Set RTL/ Tech Viewer behaves when it is initially invoked’ will pop up. Just click on the ‘OK’.

• Now a window will be opened with a diagram.

• Double click inside the box.

• Now, double click inside the AND box.

• Step 18: View for Technology Schema
  • Double click on the ‘View technology Schematic’ option.
  • A pop-up will come to click on the ‘OK’ option.

• A new diagrammatic window opened up.

•  Double Click inside the box of the diagram.

• A box will be there named – ‘lut2’. Double click on that.

It will display several diagrams.

The schematic Diagram:

• Click on the Equation to see the relation.

• Click on the Truth table to find the truth table.

• Click on the Karnaugh Map to find the Map.

Check out our other VLSI articles!

• 1. VLSI Basics
• 2. VLSI logic Design(Advanced)
• 3. Frequently Asked Interview Questions on VLSI!

Verilog Tutorial : Points of Discussion

• What is Verilog?
• History and Standardization
• Verilog Design
• Verilog Modelling
• Verilog Operators

For others topic related to Verilog Tutorial, Click Here!

What is Verilog?

Verilog is the combination of the terms “Verification” and “Logic”. It is hardware description language or a special type of programming language which describes the hardware implementations of digital system and circuits. It is a strongly typed language and points to be remembered that it is not a programming language.

For step-by-step VHDL Tutorial, Click Here!

History and Standardization of Verilog

Prabhu Goel, Chi-Lai Huang, Douglas Warmke and Phil Moorby developed the Verilog around the year 1983-1984. The first name was “Automated Integrated Design Systems” which was further renamed as “Gateway Design Automation” and was purchased by Cadence in the year 1990. Cadence is now the copyright owner of Verilog and the Verilog-XL.

Primarily, the use of Verilog was to define and to start the simulation. Later the popularity of the language raised a demand for more development, and it leads to the synthesis of the logic circuits.

Verilog Tutorial: Standardization

The popularity for VHDL forced cadence to publish the Verilog Language as open source. The first standardization of Verilog by IEEE was labelled as 1364-1995 and named as Verilog-95.

Revisions	Updates
IEEE 1364 – 2001	Verilog-2001. Supports signed variables and nest. Largely used by EDA packages.
IEEE 1364-2005	Verilog 2005. Came up with little corrections and clarifications.
IEEE P1800-2005	System Verilog.
IEEE 1800-2017	Merger of SystemVerilog and Verilog. Known as SystemVerilog 2009.

Verilog Design

Verilog has two types of design methodologies. They are – Bottom-up approach & Top-down approach.

Bottom-up Approach: It is the conventional way of designing models. The planning is implemented at the gate level. Typical gates are used for implementations. This method opens up paths for different structural and ordered planning.

Top-down Approach: This approach has some advantages over the conventional one. Changes can be made easier here. Early testing is also possible.

Verilog Modelling

Verilog modelling has some design units. Let us discuss the primary components.

A. Module

A Verilog model comes up with port declarations, data type declarations, circuit functionality, timing specifications. A basic structure of the Module is given below.

• Verilog is case sensitive.
• Reserved keywords are written in lower cases.
• A semicolon is used to terminate the statement.
• The comment rule is same as C Programming Language.
• Single line comment starts with “//”.

For example – //Example of a Verilog single line comment

• Multiline comments start with – ‘ /*’  and ends with ‘*/’.

For example –

/* Example

Of Verilog multiple

Line comment*/

• Timing specifications are used for the simulation process.

A module consists of a maximum of four levels of notion. The levels are defined below.

Behavioral: The highest level of notion. The anticipated design is planned at this level. Though, there is no thought for hardware implementations.

Dataflow: This level of Verilog Module describes the dataflow of the desired design. Hardware implementations of the dataflow through components are kept in mind while designing this level.

Gate: Logic gates are implemented in this Verilog module level. Interconnections are implemented between the gates.

Switch: The lowest level of notion. Switches, storage lumps are implemented. The interconnections are also designed between them.

B. Module Declarations

Module declarations start with ‘module’ keyword. It includes a port list (if exists).

Port types: There are three types of ports. The name and its functionality are given below.

• input – input port
• output – output port
• inout – bi-directional port

Port Declarations: The general structure for port declarations is given below.

<port_type> <port_name>;

C. Data Types

There are several kinds of data types in Verilog.

 Net Data Type: This type of data describes the physical interrelate between flows.

Nets -> Functional Block: MUX -> Functional Blocks: Adders -> Nets

The below table will provide more details about Net Datatype.

Type	Characterization
wire	Describes node or connections
tri	Describes a tri-state node
supply0	Represents Logic 0
suppy1	Represents Logic 1

•  Bus declarations: The general structure of bus declarations is given below.

<data_type> [Most Significant Bit (MSB): Least Significant Bit(LSB)] <signal_name>;

          <data_type> [Least Significant Bit(LSB): Most Significant Bit(MSB)] <signal_name>;

For example –

wire [3: 1] in;

Variable Data Type: This datatype describes the element to save a data for the time being.

There are many types of variable, supported by Verilog. Some of them are –

integer – 32 bits, Signed.

reg – any bit size, unsigned. To implement signed reg, use keyword – ‘reg signed’.

real, time, realtime – no support for synthesis.

D. Module Instantiation

After all the declarations, the module can be instantiated at a higher-level module with the help of some syntaxes. By instantiating modules, we can build designs with multiple levels of hierarchy. That will further help us to achieve simpler maintainability. Most of the modern designs have numerous layers of hierarchy.

The general format for instantiation is given below.

<componenet_name> #<delay> <instance_name> (port_list);

component name: It is the name of the module for the lower-level component.

delay: It is an optional choice. Delay introduces a delay throughout the component.

instance name: It is the exclusive name given by the designer for every individual instance.

port list: Port list gives the signal lists which will be connected to the component.

E. Simulation Component

After the designing process get completed, the testing process starts. This testing can be done using the stimulus block. Stimulus blocks are commonly known as a test bench.

Stimulus applications can be of two types. The primary design starts with the design block and directly drags the port signals into the design blocks.

The second design instantiates the stimulus block and the design block in a higher-level replica model. Interface is the communication link between the blocks.

Some Basic Verilog Concepts

Verilog Operators

Verilog has three fundamental operators for Verilog HDL. They are given below.

Unary Verilog operators : These types of Verilog operators come first of the operands.

For example: x = ~ y; Here ‘~’ is a unary operator

Binary Verilog operators : These types of Verilog operators come in-between two operands.

For example: x = y || z ; Here ‘||’ is a binary operator.

Ternary Verilog operators : These types of Verilog operators use two different operators to differentiates three operators.

For example: x = y?  z  : w; here ‘?’ and ‘:’ are ternary operators.

Verilog HDL’s categorical operators are – arithmetical, logical, relational, bitwise, shift, concatenation, and equality. Different types of Verilog operators and their symbols are given in the below table.

Type of Operator	Symbol	Operation	Operands needed
Arithmetic	*	Multiplication	Two
Arithmetic	/	Division	Two
Arithmetic	+	Addition	Two
Arithmetic	–	Subtraction	Two
Arithmetic	%	Modulus	Two
Logical	!	negation	One
Logical	&&	AND	Two
Logical	||	OR	Two
Relational	>	Greater than	Two
Relational	<	Less than	Two
Relational	> =	Greater than or equal to	Two
Relational	< =	Less than or equal to	Two
Equality	==	Equals to	Two
Equality	! =	Not equals to	Two
Equality	===	Case equal	Two
Equality	! ==	Case not equal	Two
Bitwise	~	Negation	One
Bitwise	&	Bitwise AND	Two
Bitwise	|	Bitwise OR	Two
Bitwise	^	Bitwise XOR	Two
Bitwise	~^	Bitwise XNOR	Two
Reduction	&	Reduction AND	One
Reduction	~&	Reduction NAND	One
Reduction	|	Reduction OR	One
Reduction	~|	Reduction NOR	One
Reduction	^	Reduction XOR	One
Reduction	^~	Reduction XNOR	One
Shift	>>	Right Shift	Two
Shift	<<	Left Shift	Two
Concatenation	{ }	Concatenation	Can be of any numbers
Replication	{ { } }	Replication	Can be of any numbers
Conditional	? :	Conditional	Three

Verilog Operators has precedence also. Their Precedence is given in the below table.

Operator	Symbols	Precedence
Unary Multiplication, Division, Modulus	+ ,-, !, ~ *, /, %	Highest
Addition, Subtraction Shift	+, – <<, >>
Relational Equality	<, <=, >, >= ==, !=, ===, !==
Reduction     Logical	&, ~& ^, ^~ |, ~| && ||
Conditional	?:	Lowest

Verilog Number Specifications

Verilog numbers are of two types, sized numbers and unsized numbers.

Sized Verilog numbers: The general structure for representing sized numbers in Verilog HDL is given below.

<size>’<base_format><numbers>

For example – 8’b3456;

This is a sized Verilog number which describes that it is an 8-bit number and of binary type.

• size: Size is the number of digits the main number has. Size is described using decimal values.
• base_format: Base format suggests which type of number it would be. There are several types – binary (given by – ‘b’), decimal (given by – ‘d’), octal (given by – ‘o’), hexadecimal (given by – ‘h’). If there is no specification for base_format, then by default it is a decimal number.
• numbers: The main number you want to put in.

Unsized Verilog numbers: These numbers do not require any specified size.

The general structure for representing unsized numbers in Verilog HDL is given below.

’<base_format><numbers>

For example – ’h3456;

This is an unsized Verilog number which describes that it is a hexadecimal number.

Negative Numbers: If you want to declare a number as a negative number, then put a minus symbol (-) before the number.

For example: – 345; it is a negative, unsized, decimal number.

Verilog Arrays

Arrays of integer, registers (reg), vectors ( of reg or net data types, several bit lengths) and time are possible in Verilog HDL. The basic declaration of arrays is shown below with an example.

integer matrix [0:3];

This means an array of seven values.

• Verilog doesn’t allow any array for real variables.
• Verilog HDL doesn’t support any multidimensional array.
• Array elements can be retrieved using – <array_name>[<position_of_the_element>]

For others topic related to Verilog Tutorial, Click Here!

For step-by-step Verilog Tutorial using Xilinx, Check our next article!

CONTENTS

• What is Multiplexing ?
• What are the types of Multiplexing ?
• Time Division Multiplexing (TDM)
• Descriptions of TDM
• Frequency Division Multiplexing (FDM)
• Descriptions of FDM
• TDM vs FDM

What is Multiplexing ?

Define Multiplexing:

“Multiplexing is a method where many message signs are assembled into a composite signal for the purpose of transmission through a communication channel”.

These signals are transmitted through one communication channel. The signals have to be specified so that they do not interfere with one another, and they have to be separated in the receiver end again to recreate the original signal.

Multiplexing Techniques

It is of two types as follows:

1. Time Division Multiplexing (TDM)
2. Frequency Division Multiplexing (FDM)

Time Division Multiplexing:

What is TDM?

“Time Division Multiplexing (TDM) is a technique in which a number of signals are made to pass through a common channel at different time slots.“

Diagram of TDM:

Here, the TDM technique is employed to the three analog resources that are multiplexed through a PCM system. In practice, a digital switch is utilized for its sampler. This fs = 1/Ts represents the frequency of spinning to its sampler; also fs fits the Nyquist rate for its analog sources with the maximum selective bandwidth. In the certain process where the bandwidth of these is different, the bigger bandwidth resources could be linked to many switch places onto the sampler side to be usually sampled more than the shorter bandwidth input signal.

In the receiver, the sampler needs to be connected with the processed waveform, so the PAM samples corresponding to input one will show up on the channel just only output signal. This is known as ‘frame synchronization’. Lpf has been utilized to rebuild the analogue signals in the PAM samples. ISI resulting in bad channel filtering may induce PCM samples from one communication channel to look on other station, and frame synchronization condition has been maintained. The feedthrough of a one specific communication channel into the other channel is known as cross-talk.

Advantages and Disadvantages of TDM:

Advantages of TDM

• Usually, TDM is more flexible than FDM.
• The circuit design of TDM is not complicated.
• In TDM, less cross-talk has occurred.
• Channel bandwidth length is longer.

Disadvantages of TDM

• Frequency Division Multiplexing process has no need of synchronization.
• Implementation can be complex.

Applications of TDM

• In ISDN (integrated service digital network), TDM is used.
• In PSTN (public switched telephone network), TDM is used.
• In a telephone system, TDM is widely used.
• TDM is used in telephone wire lines.

Frequency Division Multiplexing:

What is FDM?

“Frequency Division Multiplexing is a mechanism of signal transmission in which sharing the available bandwidth of a communication channel occurs among the signals to be transmitted.“

In general, FDM schemes are utilized for the analog signal applications.

Diagram of Frequency division Multiplexing:

FDM is a method of transmitting many messages concurrently through a wideband by modulating the message signals on a few subcarriers and forming a composite baseband signal. This mixed signal is dependent on the quantity of those controlled subcarriers. This mixed signal could then be modulated by AM, DSB, SSB, PM, FM, as the primary types. The type of modulation used in the subcarriers may differ, and also the type used in carrier signal could also differ.

On the other hand, the mixed signal range should consist of inputs signal that should not possess overlapping spectra; otherwise, cross-talk will happen involving the receiver end’s message signals. The mix baseband signal subsequently modulates the transmitter to create the FDM signal sent across the wideband channel.

This FDM collected and demodulated to recreate the combination baseband signal filtered through filters and modulated subcarriers. The sub-carrier has to be demodulated to reproduce the message signals such as m1(t), m2(t) etc.

A speaker with a traditional monaural FM receiver may listen to that the audio sound (composed of the remaining – and the right-channel sound ). By comparison, a speaker with a stereo recipient will get the left-channel sound on the left speaker and the right-channel sound on the ideal speaker. The gap sound is used to govern a 38-kHz DSB-SC sign. Even a 19-kHz pilot tone has been mixed into the mix baseband signal mb(t) to supply a reference sign for coherent subcarrier demodulation in receiver end. As we all know, this program can be used with present FM monaural recipients.

Advantages and Disadvantages of FDM:

Advantages of FDM

· Between the transmitter and receiver, unlike TDM, FDM does not need any synchronization.

· Through FDM, a large number of signals can be transmitted simultaneously.

· Slow, narrowband fading can only affect one single channel.

· Demodulation of FDM is much easier comparatively than TDM.

Disadvantages of FDM

• This suffers from cross-talk problem.
• In this type Communication channel must have a large bandwidth.
• In the technique, its channels get affected due to band fading.
• In FDM intermodulation distortion takes place.

Applications of FDM

• Frequency Division Multiplexing has applications in TV networks.
• FDM is used for FM & AM radio broadcasting.
• FDM was also being used in the first-generation cellular telephone.

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