Verilog Tutorial : Points of Discussion
- What is Verilog?
- History and Standardization
- Verilog Design
- Verilog Modelling
- Verilog Operators
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What is Verilog?
Verilog is the combination of the terms “Verification” and “Logic”. It is hardware description language or a special type of programming language which describes the hardware implementations of digital system and circuits. It is a strongly typed language and points to be remembered that it is not a programming language.
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History and Standardization of Verilog
Prabhu Goel, Chi-Lai Huang, Douglas Warmke and Phil Moorby developed the Verilog around the year 1983-1984. The first name was “Automated Integrated Design Systems” which was further renamed as “Gateway Design Automation” and was purchased by Cadence in the year 1990. Cadence is now the copyright owner of Verilog and the Verilog-XL.
Primarily, the use of Verilog was to define and to start the simulation. Later the popularity of the language raised a demand for more development, and it leads to the synthesis of the logic circuits.
Verilog Tutorial: Standardization
The popularity for VHDL forced cadence to publish the Verilog Language as open source. The first standardization of Verilog by IEEE was labelled as 1364-1995 and named as Verilog-95.
Revisions | Updates |
IEEE 1364 – 2001 | Verilog-2001. Supports signed variables and nest. Largely used by EDA packages. |
IEEE 1364-2005 | Verilog 2005. Came up with little corrections and clarifications. |
IEEE P1800-2005 | System Verilog. |
IEEE 1800-2017 | Merger of SystemVerilog and Verilog. Known as SystemVerilog 2009. |
Verilog Design
Verilog has two types of design methodologies. They are – Bottom-up approach & Top-down approach.
Bottom-up Approach: It is the conventional way of designing models. The planning is implemented at the gate level. Typical gates are used for implementations. This method opens up paths for different structural and ordered planning.
Top-down Approach: This approach has some advantages over the conventional one. Changes can be made easier here. Early testing is also possible.
Verilog Modelling
Verilog modelling has some design units. Let us discuss the primary components.
A. Module
A Verilog model comes up with port declarations, data type declarations, circuit functionality, timing specifications. A basic structure of the Module is given below.
module module_name (port_list);
<port_declarations>
<data_type_declarations>
<circuit_functionality>
<timing_specifications>
end module
- Verilog is case sensitive.
- Reserved keywords are written in lower cases.
- A semicolon is used to terminate the statement.
- The comment rule is same as C Programming Language.
- Single line comment starts with “//”.
For example – //Example of a Verilog single line comment
- Multiline comments start with – ‘ /*’ and ends with ‘*/’.
For example –
/* Example
Of Verilog multiple
Line comment*/
- Timing specifications are used for the simulation process.
A module consists of a maximum of four levels of notion. The levels are defined below.
Behavioral: The highest level of notion. The anticipated design is planned at this level. Though, there is no thought for hardware implementations.
Dataflow: This level of Verilog Module describes the dataflow of the desired design. Hardware implementations of the dataflow through components are kept in mind while designing this level.
Gate: Logic gates are implemented in this Verilog module level. Interconnections are implemented between the gates.
Switch: The lowest level of notion. Switches, storage lumps are implemented. The interconnections are also designed between them.
B. Module Declarations
Module declarations start with ‘module’ keyword. It includes a port list (if exists).
Port types: There are three types of ports. The name and its functionality are given below.
- input – input port
- output – output port
- inout – bi-directional port
Port Declarations: The general structure for port declarations is given below.
<port_type> <port_name>;
C. Data Types
There are several kinds of data types in Verilog.
Net Data Type: This type of data describes the physical interrelate between flows.
Nets -> Functional Block: MUX -> Functional Blocks: Adders -> Nets
The below table will provide more details about Net Datatype.
Type | Characterization |
wire | Describes node or connections |
tri | Describes a tri-state node |
supply0 | Represents Logic 0 |
suppy1 | Represents Logic 1 |
- Bus declarations: The general structure of bus declarations is given below.
<data_type> [Most Significant Bit (MSB): Least Significant Bit(LSB)] <signal_name>;
<data_type> [Least Significant Bit(LSB): Most Significant Bit(MSB)] <signal_name>;
For example –
wire [3: 1] in;
Variable Data Type: This datatype describes the element to save a data for the time being.
There are many types of variable, supported by Verilog. Some of them are –
integer – 32 bits, Signed.
reg – any bit size, unsigned. To implement signed reg, use keyword – ‘reg signed’.
real, time, realtime – no support for synthesis.
D. Module Instantiation
After all the declarations, the module can be instantiated at a higher-level module with the help of some syntaxes. By instantiating modules, we can build designs with multiple levels of hierarchy. That will further help us to achieve simpler maintainability. Most of the modern designs have numerous layers of hierarchy.
The general format for instantiation is given below.
<componenet_name> #<delay> <instance_name> (port_list);
component name: It is the name of the module for the lower-level component.
delay: It is an optional choice. Delay introduces a delay throughout the component.
instance name: It is the exclusive name given by the designer for every individual instance.
port list: Port list gives the signal lists which will be connected to the component.
E. Simulation Component
After the designing process get completed, the testing process starts. This testing can be done using the stimulus block. Stimulus blocks are commonly known as a test bench.
Stimulus applications can be of two types. The primary design starts with the design block and directly drags the port signals into the design blocks.
The second design instantiates the stimulus block and the design block in a higher-level replica model. Interface is the communication link between the blocks.
Some Basic Verilog Concepts
Verilog Operators
Verilog has three fundamental operators for Verilog HDL. They are given below.
Unary Verilog operators : These types of Verilog operators come first of the operands.
For example: x = ~ y; Here ‘~’ is a unary operator
Binary Verilog operators : These types of Verilog operators come in-between two operands.
For example: x = y || z ; Here ‘||’ is a binary operator.
Ternary Verilog operators : These types of Verilog operators use two different operators to differentiates three operators.
For example: x = y? z : w; here ‘?’ and ‘:’ are ternary operators.
Verilog HDL’s categorical operators are – arithmetical, logical, relational, bitwise, shift, concatenation, and equality. Different types of Verilog operators and their symbols are given in the below table.
Type of Operator | Symbol | Operation | Operands needed |
Arithmetic | * | Multiplication | Two |
Arithmetic | / | Division | Two |
Arithmetic | + | Addition | Two |
Arithmetic | – | Subtraction | Two |
Arithmetic | % | Modulus | Two |
Logical | ! | negation | One |
Logical | && | AND | Two |
Logical | || | OR | Two |
Relational | > | Greater than | Two |
Relational | < | Less than | Two |
Relational | > = | Greater than or equal to | Two |
Relational | < = | Less than or equal to | Two |
Equality | == | Equals to | Two |
Equality | ! = | Not equals to | Two |
Equality | === | Case equal | Two |
Equality | ! == | Case not equal | Two |
Bitwise | ~ | Negation | One |
Bitwise | & | Bitwise AND | Two |
Bitwise | | | Bitwise OR | Two |
Bitwise | ^ | Bitwise XOR | Two |
Bitwise | ~^ | Bitwise XNOR | Two |
Reduction | & | Reduction AND | One |
Reduction | ~& | Reduction NAND | One |
Reduction | | | Reduction OR | One |
Reduction | ~| | Reduction NOR | One |
Reduction | ^ | Reduction XOR | One |
Reduction | ^~ | Reduction XNOR | One |
Shift | >> | Right Shift | Two |
Shift | << | Left Shift | Two |
Concatenation | { } | Concatenation | Can be of any numbers |
Replication | { { } } | Replication | Can be of any numbers |
Conditional | ? : | Conditional | Three |
Verilog Operators has precedence also. Their Precedence is given in the below table.
Operator | Symbols | Precedence |
Unary Multiplication, Division, Modulus | + ,-, !, ~ *, /, % | Highest |
Addition, Subtraction Shift | +, – <<, >> | |
Relational Equality | <, <=, >, >= ==, !=, ===, !== | |
Reduction Logical | &, ~& ^, ^~ |, ~| && || | |
Conditional | ?: | Lowest |
Verilog Number Specifications
Verilog numbers are of two types, sized numbers and unsized numbers.
Sized Verilog numbers: The general structure for representing sized numbers in Verilog HDL is given below.
<size>’<base_format><numbers>
For example – 8’b3456;
This is a sized Verilog number which describes that it is an 8-bit number and of binary type.
- size: Size is the number of digits the main number has. Size is described using decimal values.
- base_format: Base format suggests which type of number it would be. There are several types – binary (given by – ‘b’), decimal (given by – ‘d’), octal (given by – ‘o’), hexadecimal (given by – ‘h’). If there is no specification for base_format, then by default it is a decimal number.
- numbers: The main number you want to put in.
Unsized Verilog numbers: These numbers do not require any specified size.
The general structure for representing unsized numbers in Verilog HDL is given below.
’<base_format><numbers>
For example – ’h3456;
This is an unsized Verilog number which describes that it is a hexadecimal number.
Negative Numbers: If you want to declare a number as a negative number, then put a minus symbol (-) before the number.
For example: – 345; it is a negative, unsized, decimal number.
Verilog Arrays
Arrays of integer, registers (reg), vectors ( of reg or net data types, several bit lengths) and time are possible in Verilog HDL. The basic declaration of arrays is shown below with an example.
integer matrix [0:3];
This means an array of seven values.
- Verilog doesn’t allow any array for real variables.
- Verilog HDL doesn’t support any multidimensional array.
- Array elements can be retrieved using – <array_name>[<position_of_the_element>]
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