39 Important VLSI, VHDL & Verilog Interview Q&A

VLSI, VHDL, Verilog Interview Questions

1. Give the full term of VHDL.

1. Very High Definition Language
2. Very High Speed Integration Hardware Description Language
3. Very High Description Language
4. Very High Speed Scaling Hardware Describing Language

Ans: 2) Very High Speed Integration Hardware Description Language

For basic VHDL Tutorials, Click Here!

2. What is the number of Metal Oxide Filed Effect Transistors are needed to construct a Bi-complementary metal Oxide Semiconductor NOR gate which have two input?

1. 5 MOSFETs
2. 6 MOSFETs
3. 7 MOSFETs
4. 8 MOSFETs

Ans: 3) 7 MOSFETs

“How a Logic gate is designed in VLSI?” Find the answer here!

3. What is the effect of ‘Delay’ if the power supply voltage gets increased?

1. Increases
2. Decreases
3. Remains the same
4. Delay has nothing o do with power supply.

Ans: 2) Decreases

4. Which is true about VLSI design?

1. VLSI is a sequential process which has feedback loops.
2. VLSI is a parallel process which has no feedback loops.
3. VLSI is both sequential and parallel process that has feedback loops.
4. VLSI is a sequential process which has no feedback loops.

Ans: 3) VLSI is both sequential and parallel process that has feedback loops.

For more details about Verilog Interview Questions and other topic like VLSI Design, Check this!

5. What is the use of CAD tools in VLSI design?

1. It automates the VLSI design.
2. It reduces the design cycle time.
3. It reduces the chance of errors.
4. All of the above.

Ans: 4) All of the above.

6. Which type of product is more suitable for FPGA based Design?

1. Large scale product development.
2. High Speed applications.
3. Prototype development.
4. Low power applications.

Ans: 3) Prototype development.

What is Verilog? What is system Verilog? and other Verilog Interview Questions and Answers are here!

7. What is the relation between interconnect delay and gate delay?

1. The Relation is technology dependent.
2. Gate delay always more than interconnect delay.
3. Interconnect delay always more than the gate delay.
4. They are same.

Ans: 1) The relation is technology dependent.

8. State True or False

Statement: For a Y chart, the details of design information increases when moved from the centre to the periphery.

1. True
2. False

Ans: (2). False

9. Why a short channel device is preferred?

1. It is easier for fabrication.
2. It has lower power consumption.
3. It has high speed.
4. It has better output characteristics.

Ans: 3) It has high speed.

10. Where does the subthreshold operation of MOSFET find applications?

1. Memories.
2. Charge coupled devices.
3. Biomedical applications.
4. None of the above.

Ans: 3) Biomedical applications.

Make your First VHDL Project!

Click Here!

VLSI, VHDL, Verilog Interview Questions, Image – 1

11. What is the relation between the ON-resistance of MOSFET and gate to source voltage (Vgs)?

1. ON-resistance linearly increases with Vgs.
2. ON-resistance linearly decreases with Vgs.
3. ON-resistance exponentially increases with Vgs.
4. ON-resistance non-linearly decreases with Vgs.

Ans: 4) ON-resistance non-linearly decreases with Vgs.

12. What is the threshold voltage of an EMOSFET?

1. Equal to 0 V.
2. Less than 0 V.
3. Greater than 0 V.
4. None of the above.

Ans: 3) Greater than 0 V.

13. Find the odd one out.

1. Channel length modulation
2. Subthreshold Conduction
3. Hot carrier effect.
4. Body Effect

Ans: 4) Body effect. (All the other options are 2^nd order effect).

14. How does doping density change for constant voltage scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 2) Increases by a factor of s2.

15. How does power dissipation occur for full scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 3) Decreases by a factor of s2.

16. How does power dissipation occur for constant voltage scaling?

1. Increases by a factor of s
2. Increases by a factor of s2.
3. Decreases by a factor for s.
4. Decreases by a factor for s2.

Ans: 1) Increases by a factor of s.

17. What is the main advantage of depletion load NMOSFET inverter over EMOSFET load?

1. Less power dissipation
2. Easier fabrication process
3. Sharper Vtc transitions and better noise margins.
4. None of the above.

Ans: 3) Sharper Vtc transitions and better noise margin.

18. Why is polysilicon used for the gate in MOSFET?

1. Because it is a semi-metal.
2. Because it has lattice matching with Silicone
3. Because it is easier to fabricate.
4. None of the above.

Ans: 2) Because it has lattice matching with silicone.

19. State True or False

Statement: In full scaling, the magnitude of the electric field is constant.

1. True
2. False

Solution: (1). True

20. Which of the given statement is true regarding a MOSFET inverter?

1. One PMOSFET and one resistor are needed to implement a MOSFET inverter.
2. One NMOSFET and one resistor are needed to implement a MOSFET inverter.
3. Two PMOSFETs.
4. Two NMOSFETs.

Ans: 2) One NMOSFET and one resistor is needed to implement a MOSFET inverter.

Build your first Verilog project!

See also  Active Low Pass Filter:13 Facts Most Beginner's Don't Know!

Click here!

VLSI, VHDL, Verilog Interview Questions, Image – 2

21. On which factors, the power dissipation of a CMOS inverter depends?

1. Supplied Voltage.
2. NMOSFET’s channel width.
3. PMOSFET’s channel width.
4. All of the above.

Ans: 1) Supplied Voltage

22. State True or False

Statement: The PMOS transistors act as Pull-up network in a CMOS inverter.

1. True
2. False

Solution: (1). True

23. Which of the following effect has no contribution to deviate the ideal situation of a current mirror circuit?

1. DIBL effects.
2. Threshold offset between two transistors
3. Channel length modulation
4. Imperfect geometrical matching.

Ans: 1) DIBL effects.

24. What does the ASIC cell library contain?

1. The physical layout of the cells
2. Routing model of the cells
3. Timing model of the cells
4. All of the above.

Ans: 1) Physical layout of the cells.

25. Why does lowest propagation delay occur through a gate?

1. Due to – strong transistor, high temperature, high voltage.
2. Due to – strong transistor, low temperature, high voltage.
3. Due to – Weak transistor, high temperature, high voltage.
4. Due to – weak transistor, low temperature, low voltage.

Ans: 3) Due to – Weak transistor, high temperature, high voltage.

26. Which of the following is true about VLSI logic design?

1. VLSI minimizes the area and delay
2. VLSI minimizes the area at the cost of delay
3. VLSI maximizes speed by decreasing area
4. VLSI minimizes delay by reducing the area

Ans: 2) VLSI minimizes the area at the cost of delay.

27. What is a hard macro?

1. Flexible Block
2. Fixed Block
3. Flexible block with a fixed aspect ratio
4. Flexible block with a flexible aspect ratio

Ans: 2) Fixed Block

28. State True or False

Statement: The full form of SPICE is – Simulation Program with Integrated Circuit Emphasis.

1. True
2. False

Solution: (1). True

29. What is the equivalent circuit for CMOS comparator?

1. Uncompensated CMOS OPAMP.
2. Compensated CMOS OPAMP.
3. Partially Compensated CMOS OPAMP.
4. None of the above is true.

Ans: 1) Uncompensated CMOS OPAMP.

30. What is the relation between the equivalent resistance of a switched capacitor and the clock frequency?

1. The resistance is proportional to clock frequency.
2. The resistance is inversely proportional to clock frequency.
3. The resistance is proportional to the square of the clock frequency.
4. The resistance is inversely proportional to the square of the clock frequency.

Ans: 2) The resistance is inversely proportional to clock frequency.

30 Most important and frequently asked VLSI Interview Questions! Click Here!

VLSI, VHDL, Verilog Interview Questions, Image – 3

See also  Equivalent Von Mises Stress: What, How, Examples, Exhaustive Facts

31. What is the relation between the equivalent resistance of a switched capacitor and the capacitance?

1. The resistance is proportional to the capacitance.
2. The resistance is inversely proportional to the capacitance.
3. The resistance is proportional to the square of the capacitance.
4. The resistance is inversely proportional to the square of the capacitance.

Ans: 2) The resistance is inversely proportional to the capacitance.

32. What is the condition for domination by Diffusion Current?

1. Strong Inversion
2. Weak Inversion
3. Both Strong and weak inversion.
4. Cannot be determined.

Ans: 2) Weak Inversion.

33. What is the condition for domination by Drift Current?

1. Strong Inversion
2. Weak Inversion
3. Both Strong and weak inversion.
4. Cannot be determined.

Ans: 1) Strong Inversion.

34. State True or False

Statement: In the cascode current mirror, the output resistance is increased.

1. True
2. False

Solution: (1). True

35. State True or False

Statement: A current mirror circuit can be used as a current amplifier by increasing the (W/L) ratios of the mirrored and source MOSFET

1. True
2. False

Solution: (1). True

36. Which connections of NMOS in PDN, help to realize the AND terms?

1. Cascade Connection
2. Anti – parallel Connections
3. Series Connections
4. Parallel Connections

Ans: 3) Series Connections

37. Which type of transistor can pass logic-high value perfectly, but not the logic-low value?

1. NMOSFET
2. PMOSFET
3. CMOS
4. None of the above

Ans: 2) PMOSFET

38. What is the minimum number of transistors needed to design an XOR gate?

1. Three
2. Four
3. Five
4. Six

Ans: 4) Six

39. Which type of logic design provides the minimum propagation delay?

1. Emitter Coupled Logic
2. Transistor Transistor Logic
3. Register Transistor Logic
4. Diode Transistor Logic

Ans: 1) Emitter Coupled Logic

40. State True or False

Statement: Dynamic CMOS logic operates using two non-overlapping clock pulses.

1. True
2. False

Solution: (2). False.

For more VLSI related topic and Verilog interview questions click here

Sudipta Roy

Hi, I am Sudipta Roy. I have done B. Tech in Electronics. I am an electronics enthusiast and am currently devoted to the field of Electronics and Communications. I have a keen interest in exploring modern technologies such as AI & Machine Learning. My writings are devoted to providing accurate and updated data to all learners. Helping someone in gaining knowledge gives me immense pleasure.
Let’s connect through LinkedIn –