VHDL Tutorials | VHDL Process | It’s important concepts

In this VHDL Tutorial, we will discuss some of the basic concepts related to VHDL technology and few example with coding. VHDL Tutorial is segmented as follows :


A. What is VHDL?

B. History and Standardization

C. VHDL Design Procedures

D. Some rules and basic information about VHDL

E. Syntaxes & Some important concepts for writing VHDL Codes

F. VHDL Simulators for VHDL Tutorial

VHDL Tutorial
VHDL Tutorial, Image – 1, Image Credit – XilinxInc, Ingeniería electrónica eléctricaCC BY-SA 4.0

VHDL || What is VHDL?

The full form of VHDL stands for Very High Speed Integrated Circuit Hardware Description Language (VHSIC-HDL).

As the name suggests, VHDL is a hardware description language or a special type of programming language which describes the hardware implementations of digital system and circuits.  It is a strongly typed language and points to be remembered that it is not a programming language.  

History and Standardization

US Defense Department has a significant contribution to the modern technological field. It has given birth too many great ideas and innovations. US Defense also developed VHDL in the year 1983. It was developed for documentation of behavior of the application specific integrated circuits.

Later, some ideas were implemented from Ada programming languages. VHDL got standardized for the first time in the year 1987. It was added up with several data types of several types, including strings and numeric and logical.


VHDL or for Very High Speed Integrated Circuit Hardware Description Language (VHSIC-HDL) is standardized by IEEE 1076 standard. It is being updated from its birth and has undergone many revisions. Let us look at some of the standard revisions and major updates.

IEEE 1076 – 1987Revision and standardization from US Defense.
IEEE 1076 – 1993Came up with the greatest release, and it is the most widely used version.
IEC 61691 -1 – 1- 1: 2004IEC adopted IEEE 1076-2002 Version
IEEE 1076 -2008Updated with some major changes like – Introduction of generics on packages and use of external names
IEC 61691 -1 – 1- 1: 2011IEC adopted IEEE 1076-2008 Version
Check the standardization here, VHDL Tutorial Table – 1

Design of VHDL

VHDL design has some design units. They are known as – Entity, Architecture, Configuration, and Package.

Entity: Entity defines external views of a model that is a symbol.

Architecture: Architecture defines the functionality of a model that is schematic.

Configuration: Configuration is used for associating architecture with an entity.

Package: Package is the collection of information which can be referenced by VHDL modules. A VHDL package consists of two part. They are – package declaration and package body.

A basic code designed in VHDL Tutorial, Image Credit – Vhdl_signed_adder.pngRevRagnarok derivative work: Bernard LadenthinVhdl signed adder sourceCC BY-SA 3.0

Entity Declaration

The general structure of entity declaration is given below –

ENTITY < entity_name > IS

          Generic declarations

          Port declarations

END ENTITY <entity_name>;

  • <entity_name> can be alphabetic/ numerical or alpha-numerical.
  • Generic Declarations is for passing information into a model.
  • Port Declarations is for describing the inputs and outputs pins.
  • An entity can be closed in several ways.
    • END ENTITY <entity_name>;
    • END;

Port Declarations

A general structure for port declarations is given below –

ENTITY < entity_name > IS

          Generic declarations

          — Port Declarations:


          SIGNAL CLK, CLR: IN BIT;

          q: OUT BIT

          — note that there is no semicolon in the last line of declarations.


END ENTITY <entity_name>;

The structure of port declaration: <class> object_name : <mode> <type>;

  • Class: Class is what can be done to an object. Here class is signal. A point to be remembered that the SIGNAL is not written while writing program; rather, it is assumed and not required.
  • Object_name: It is the identifier.
  • Mode: It specifies the direction.

IN – Input

OUT – Output

INPUT – Bidirectional

BUFFER – Output with internal feedback

  • Type: Type specifies what can be contained inside an object.

Generic Declarations

A general structure of generic declarations is given below –

ENTITY <entity_name> IS

          GENERIC (

                    CONSTANT tplh, tphl : time := 5 ns;

                    tphz, tplz : TIME := 3ns;

                    default_value : INTEGER := 1;

                    cnt_dir : STRING := “UP”

                    — note that there is no semicolon in the last line of declarations.


          Port declarations

          END ENTITY <entity_name>;

  • Generic values can be overwritten during compilation.
  • Generic must possess the tenacity to a constant during the compilation of a program.  

Note that CONSTANT keyword is assumed and not required to write.


  • Analogy-schematic: Analogy schematic gives the description of the functionality of a model and the timing associated with it.  
  • The architecture of a model should be associated with an ENTITY.
  • An Entity may have many architectures associated with it.
  • Architecture statements execute concurrently.
  • Some styles of architecture –
  • Behavioural: Behavioural model describes how designs operate.

RTL: RTL describes how designs can be implemented using registers.

Functional: It includes no timing.

  • Structural: Implementation of gate level structure.
  • Dataflow: Implementation of the truth table.
  • Architecture is ended with –
    • END ARCHITECTURE <architecture_name>;
    • END;

A general structure of writing an architecture:

ARCHITECTURE <identifier> OF <entity_identifier> IS

          SIGNAL signal_1 : INTEGER := 1;

          CONSTANT cnst := BOOLEAN := true;

          TYPE process IS (W, X, Y, Z);

          — Attribute declarations

          — Attribute specifications

          — Subprogram declarations

          — Subprogram body


          Process statements

          Concurrent procedural calls

          Signal assignment

          Generate statements

END ARCHITECTURE <identifier>;

RTL Schematic of an AND Gate, from VHDL Tutorial


As discussed, an earlier configuration is used for associating architecture with an entity. Associating or combining is necessary because An ENTITY can not work until the architecture is associated with it.  A general structure of configuration is given below.

CONFIGURATION  < identifier > OF < entity_name > IS

          FOR < architecture_name >

                    FOR < instance_name > : < component_name > USE < entity >(< architecture >)

                    END FOR;

                    FOR < instance_name > : < component_name > USE < configuration_name >

                    END FOR;

          END FOR;

END CONFIGURATION < identifier >;


VHDL packages are one whole unit of an entire system. It is the main aim of the implementation of VHDL. A package has two parts. As said earlier, package declarations and package body make a complete package.

VHDL delivers two in-built packages.

Some rules and basic information about VHDL Tutorial

Let us discuss about have a glance at some basic information before we dive to explore the VHDL tutorial.

1. Reserved Keywords: VHDL has some keywords as reserved (that cannot be used for declaring a variable).

2. Parts: VHDL has two steps or parts for the creation of a model. One is Simulation, and the other is synthesis and simulation.

3. Case sensitive language: VHDL is not a case sensitive language (for the most of the part).

4. Commenting: To comment a statement in the VHDL code editor, start the sentence with –, for an example:

— This is a comment in VHDL.

5. Termination: VHDL codes and each single lines of codes are terminated using a semicolon (whenever needed). 

6. Space Sensitivity: VHDL is not white space sensitive.

Syntaxes and Some important VHDL Tutorial concepts for writing a VHDL Codes

  1. Array with examples
  2. Process with examples
  3. IF – THEN – ELSIF implementation with examples.
  4. CASE statement

A. Array

Array stores value. It is a user-defined data type to store value. An array may contain variables of signal, constants type.

A general structure to declare an array is given below:

TYPE array_name IS ARRAY (range) OF data_type;

For an example,

TYPE lambdageeks IS ARRAY (0 to 9) OF std_logic_vector (0 UPTO 9);

B. Process Statement

Process is a simultaneous and synchronized statement. It introduces the chronological statements. Multiple processes run parallelly if the model needed.

A process consists of two parts. They are the execution of the process and then wait for the next condition.


process sensitivity_list




end process;

C. IF – THEN – ELSIF implementation

These statements are used for implementing a condition and for their result.

An if condition can have an infinite number of branches as per the requirement. A considerable number of elsif condition is also possible. But, in an, if loop, there can be only one else condition. An if loop is terminated by the end if statement. If the condition is given is true, then it will enter the loop and will execute the statement. If it fails, then go for else or elsif statement.

The syntax of the statements is given below.


          if conditional_boolean_expression then


          elsif conditional_boolean_expression then


          . . .



          end if;

D. CASE Statement

Case statement finds out which statement will be executed. A case statement can also be branched as IF-ELSE loops.


[label]: case < conditional-expression > is

          when < choice> = >


          when <choice> = >



          when <choice> = >


end case [label];

E. FOR Loop

A for loop is a continuous execution of statements according to the bounding conditions.

For each FOR loop, we need an iterator which will perform the operations in the for a loop. It is also known as an identifier. It is an integer by default and no need to declare the iterator. It is one of the most commonly used loops for making complex models. It is more familiar than while loops.


[label]: for iterator in range loop




          Statement n

end loop [label];

VHDL Simulators for VHDL Tutorial

Some of the famous VHDL simulators used for the implementation of VHDL are listed below.

  1. Xilinx Vivado: The most famous simulator for VHDL is Xilinx Vivado. Xilinx provides programmable logic devices. We will use this simulator for the next part of the VHDL Tutorial. 
  2. Cadence Incisive: The previous version was known as NC-VHDL.
  3. VHDL Simili: Symphony EDA develops it. It is free for consumers. 
  4. GHDL: One of the famous free VHDL simulator. 
  5. Boot: Freerangefactory organization developed the simulator. 
  6. NVC: Nick Gasson developed the opensource VHDL compiler. 
  7. EDA Playground: Another free version based on web-browser. 
  8. Synopsis VCS-MX.
Simulators for VHDL, We will use XILINX for our VHDL Tutorial Image Credit – ™/®Xilinx, Inc., Xilinx logo, marked as public domain, more details on Wikimedia Commons

Make your first project using VHDL. Check out the next part of VHDL Tutorial.

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About Sudipta Roy

I am an electronics enthusiast and currently devoted towards the field of Electronics and Communications.
I have a keen interest in exploring modern technologies such as AI & Machine Learning .
My writings are devoted towards providing accurate and updated data to all learners.
Helping someone in gaining knowledge gives me immense pleasure.

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