17. No of hardware interrupt request, a solitary interrupt- controller namely IC8259A could process?
Eight
Nine
Sixteen
Sixty four
Answer – (1)
18. The interrupt mask in the 8085 microprocessor is set or reset by the software instruction
By the EI interrupt
By the DI interrupt
By the RIM interrupt
By the SIM interrupt
Answer – (4)
19. For 8085, The vector address corresponding to software interrupt RST 7.0 is
0017 Hex
0027 Hex
0038 Hex
0700 Hex
Answer – (3)
20. Which one has the highest priority out of these
TRAP
RST 7.5
RST 6.5
HOLD
Answer – (4)
21. Which one of the following is the software interrupt of 8085 ?
RST 7.5
EI
RST 1.0
TRAP
Answer – (3)
22. Let the accumulator content 4F after execution the RAL instruction, contain of accumulator will be
9E
8B
8C
Answer – (1)
23. The clock’s interrupt-handler of a certain computational machine needs 2 m/sec per clock tick. The clock’s frequency is 60 Hz. What percent of the CPU is dedicated to the clk?
1.2
7.5
12
18.5
Answer – (3)
24. For “JZ NEXT” instruction, which of the following register’s memory is checked to verify if it is ‘0’ or not ?
A
B
R1
R2
Answer – (1)
25. At any time POP H instruction is performed
Data bytes in the HL pairs will be put in storage of the stack’s registers
Two data bytes are transferred to the HL pair’s register
Two data bytes at the top of the stack are moved to the CPU
Answer – (2)
26. In microprocessor instruction STA 9000H is
A data transfer instruction
A Logical instruction
A I/O and MPU will execute
Not an option
Answer – (1)
27. The addressing method in microprocessor used in the STAX B is
A Direct addressing method
A Resister addressing method
An Immediate addressing method
Register indirect addressing method
Answer – (4)
28. When a subroutine is called the address of the instruction next to CALL is kept in
The Stack
The Program counter
The Stack pointer register
Not an option
Answer – (1)
29. Machine cycles for IN instructions in microprocessor are
Eight
five
four
three
Answer – (4)
30. The instruction MOV A, B is kind of
the Immediate addressing mode
Directing addressing mode
Implied addressing mode
Register addressing mode
Answer – (4)
31. How many T-states would be required for the execution of CALL 2000 H instruction?
10
13
18
None of these
Answer – (3)
32. The number of I/O lines for 8255 chip is
256
512
1024
2K
Answer – (1)
33. How many flag registers are available in the 8051 chip?
9
8
6
5
None
Answer – (5)
34. The “programmable interval timer” is
8253 chip
8251 chip
8250 chip
8275 chip
Answer – (1)
35. The 8086 microprocessor addressing capacity is
“Addressing mode is the way to specify a particular data to be operated by an instruction.”
We need different types of addressing mode because it provides flexibility to the programmer to access data.
What are the types of Addressing Mode in 8086?
The different types of Addressing Modes are explained below:
Register Addressing:
The operand is a register.
Example – MOV, AX, BX
Immediate Addressing:
The instruction itself comprises the operands.
Example – MOV, AX, 5000H
Direct Addressing:
The instruction specifies the address the operand.
Example – MOV, AX, 9000H
Indexed Addressing:
The operand is specified using one of SI and DI as index register, along with an optional offset. The address of operand is acquired by addition of the information of the index register with the offset, if present.
Example – MOV AX, [SI] or MOV AX, [SI+1000H]
Based Addressing:
The operand is specified using one of BX and BP as base register, along with an optional offset. The address of operand is acquired by addition of the information of base register with the offset, if present.
Example – MOV AX, [BX] or MOV AX, [BP+1000H]
Based-Indexed Addressing:
The operand is specified using one of SI and DI as index register and ones of BX and BP as base register, along with an optional offset. The address of the operand is acquired by addition of information of the index register with the contents of the base register and the offset, if present.
Example – MOV AX, [SI+BX] or MOV AX, [DI+BP+1000H]
Different Flags in 8086 Microprocessor:
S (Sign Flag) – Set when answer of computation is negative.
Z (Zero) – Set when computation of previous instruction is zero.
P (Parity) – Set when lower byte contains even number of ones.
C (Carry) – When there have carry in computation.
T (Trap) – when processor enters single step instruction mode.
I (Interrupt) – Maskable interrupts are identified.
D (Direction) – In string manipulation.
AC (Auxiliary Carry)
O (Overflow) – When result is larger to accommodate in registers.
Register Flag
Pipeline Architecture in 8086 Microprocessor:
The fundamental idea of pipelined architecture is to sub divide the processing of a computer instructions into a series of independent stage (like “pre-fetch”, “fetch”, “decode”, “execute” etc.) with storage at the end of each step.
This permits the computer’s control to instruct the processing speed of the slowest step that is a lot quicker than the time requirement to do all steps at the same time. The pipeline signifies how every step is taking information simultaneously, and any step is linked to subsequent one.
In this, there are 2 separate units
– The “Bus Interface Unit” (BIU)
– The “Execution Unit” (EU).
The BIU executes all bus operations for the execution unit. The data is in communication in between the CPU and memories and input output kit upon request from the EU. During this if the EU is active implementing commands, the BIU “look ahead” and brings more instruction from the memory. This way, a type of “Fetch-Execute-Pipeline” is implemented in 8086.
Write down some of the Advantages and Disadvantages of Pipelining?
The advantages of pipelining are:
• The cycle time of the chip is comparatively lesser. Pipelining does not minimize the time necessary to finish an instruction; rather it raises the quantity of instructions which may be processed concurrently and reduces the delay between complete instructions.
• The multiple no increased pipeline stages means that more commands could be processed at once and the less delay in between the commands. Every overriding simulated microprocessor manufactured today uses at least two stage pipelines around 30- 40 stages.
• When pipelining is employed, the CPU ALU designed to work fast, but with more complicated design.
• Pipelining in concept improves the performance within an un-pipelined core by a factor stage no and also the code is impeccable for pipeline implementation.
•Pipelined CPUs in general work at a much higher clock frequency than the RAM and that improves overall processor performances.
The disadvantages of pipelining are:
This is a non-pipelined chip, simpler in design and more economical to fabricate, implements just a single instruction at a time. This avoids when sequential instructions being executed simultaneously.
This type of processor have more instruction latency in comparison to some non-pipelining chip. The operation of a pipelined processor is a lot more difficult to predict and might vary widely for various applications.
What are the functions of BIU and EU 8086 microprocessor?
Define Execution Unit (EU):
The execution unit of the 8086 and 8088 are indistinguishable. A 16-bit ALU in the EU keep up the CPU status and control flag, and deploys the general registers and instruction operand etc. All registers and datapaths from the EU are all 16 bits length for internal communications.
The EU does not have any link to the machine BUS, the external world. This acquires directions from the BIU via queue. Similarly, as soon as an instruction needs accessing memory or peripherals, the EU asks the BIU to access or to keep the information. The BIU, however, relocate address to provides the EU entry to the entire storage.
Define Bus Interface Unit (BIU):
The BIUs are employed differently to match the arrangement, performance features of various buses. The BIU implements all the bus operation for EU.
The queue size in BIU lets it maintain the EU provided with pre-fetched Instructions under most states without monopolizing the system bus. The 8086 BIU normally gets two bytes per fetching; in case a program 1 byte in the odd address and start again fetching two-byte words in the consequent even one.
Memory Segmentation in 8086 Microprocessor:
Microprocessor 8086 has 20 address pins, so maximum numbers of memory location, which can be connected with 8086 are 220 = 1MB location or 16 blocks of 64 K locations. The memory connected with 8086 divided into following four segments:
Code Memory Segment: It is used to store instructions code of a program.
Data Memory Statement: It is used to store data bytes/words.
Extra Memory Segment: It is an additional segment for storing data.
Stack Memory Segment: It is used to store stack of data using PUSH/POP instruction.
“A microcontroller is a small computer that consists of processor, internal RAM, ROM or flash, timers, interrupt handler, serial interface, ports & other application-specific devices.”
A microcontroller is employed if the memory prerequisite for computations is small and the programs and ports are used for the control and communication purpose.
For example i.e., 8051, PIC and ARM are the standard Microcontrollers.
8-bit ALU and Accumulator, 8 bit registers, 8 bit data bus and 2×16 bit address bus/program counter/data pointer and related 8/11/16 bit operations.
Fast interrupt with operational register.
Power saving mode.
Addressing Mode of 8051 Microcontroller:
“An addressing mode denotes by what method addressing a particular memory location.”
There are five important addressing modes in 8051 microcontroller, they are:
Each of these addressing modes provide important flexibility.
Immediate Addressing
Immediate addressing is like the data to be stored in memory instantly as per the opcode . The instruction itself commands which value might be kept in memories specifically.
E.g., the instruction as follows:
MOV A, #20H
Here memonics utilizes immediate addressing for the reason that the accumulator is going to be filled with the value which mentioned.
In direct addressing, the value to be loaded is time dependent, this adressing certainly not flexible.
Indirect Addressing
Indirect addressing is a really good comparatively that in most instances contributes an exceptional degree of flexibility. This is by only means to get the additional 128 bytes of internal RAM located in an 8051. Example is like
MOV A, @R0
This instruction bases the 8051 Microcontroller to have another look at the value of the R0 register. The 8051 will then load the accumulator with the info of internal RAM that’s located at the address indicated by R0 register.
By way of instance, let us say R0 retains the value 50H and address 50H retains the value 66H. When the above-mentioned instruction is implemented the 8051 will assess the value of R0. Since R0 retains 50H, the 8051 will find the value of this internal RAM address 50H and keep it in the accumulator. Indirect addressing consistently identifies internal RAM; it refers to a SFR
External Direct
External memory is get into by means of a set of instructions uses ‘external direct’ addressing. There are two such types of commands that could be used for external direct addressing operations, those are
MOVX A, @DPTR
MOVX @DPTR, A
Here, the two controls use DPTR. In these commands, DPTR should first be loaded using the location of external memory which is to be read or write. After DPTR retains the proper external memory card, the initial command will transfer the contents of the external memory address to the accumulator. The next command is going to do the contrary; it permits to write the accumulator’s value to the external memory address which is already pointed by DPTR.
External Indirect
External memory may be acquired using a indirect addressing that is known as external indirect addressing. This kind of addressing is generally utilized in relatively minor tasks which have a rather modest number of external RAM. Such example is
MOVX @R0, A
The value of R0 has to be read and the value of the accumulator is from external RAM location. Considering that the value of R0 could simply be 00 through FFh, and is limited to 256 bytes. Employing external indirect addressing; nonetheless, it’s normally simpler to use external direct mode if the task has more than 256 bytes.
Architecture of 8051 Microcontroller:
8051 is equipped with an 8-bit CPU with a Boolean processor.
5 interrupts. 2 Externals, 2 priority levels.
This has two sixteen bit timer/counters.
One programmable full-duplex serial port.
Total 32 I/O lines.
Equipped with the 4 KB of on-chip ROM ; EPROM is also available in some models.
128 bytes of on-chip RAM, just enough for many single chip.
These pins generaly utilized as I/P or O/P according to the user requirements.
PIN 9:
This is utilized as Resetting purpose; Generally HL signal pin halts the MCU and clear all the registers. When this pin is back to LO, new program will start.
PIN 10 – 17:
These are utilized as with the port 1, each of these pins could be employed as universal i/p or o/p.
Pin 10:
RXD- Ac as a serial I/P for the asynchronous trasfer otherwise clock output for synchronous mode of operation.
Pin 11:
TXD- Act as a serial O/P for the asynchronous transfer otherwise clock output for synchronous mode of operation.
Pin 12:
INT0- This is for input interrupt 0
Pin 13:
INT1- This is for input interrupt 1
Pin 14:
T0- This is employed for clock input of the timer 0
Pin 15:
T1- This is dedicated for clock input of the timer 1
Pin 16:
WR- This is for write operation controlling from external RAM memory device.
Pin 17:
RD- This pin is dedicated for read operation to external RAM memory
PIN 18-19:
X2 and X1- These are for input and output operation of the internal oscillator
PIN 20:
GND- Ground ; This is for grounding the chip.
PIN 21-28:
Port 2- provisional external memory is not present, Port 2 will work as an universal I/O operation.
PIN 29:
PSEN: MCU triggers after reading each byte from the program memory. When an external memory is employed for program storage purpose, then PSEN will be associated with the control operation.
PIN 30:
ALE: This will have important function before external memory reading, MCU will send the lower byte of the address registers to the Port-P0 and triggers the output ALE.
PIN 31:
EA: The LOW signal refer to the Port- P2 and P3 for transporting addresses irrespective of the memory status.
PIN 32-39:
Port 0: analogous to port 2, pins of port 0 could be utilized as universal I/O. The P0 performs as address O/P if ALE pin is at high state.
PIN 40:
VCC:This is for +5V dc power supply.
Interrupts of 8051 microcontroller:
Five interrupts are provided in 8051. Three sets automatically by internal operations and other two is triggered by external signal linked to pins INT0 and INT1.
Automatic interrupts are:
Timer Flag 0
Timer Flag 1
Serial Port Interrupt (R1 or T1)
Interrupt NameInterrupt Address
Timer Flag o 0 0 0 B
Timer Flag 1 0 0 1 B
INT0 0 0 0 3
INT1 0 0 1 3
Serial Input R1/ T1
Applications of Microcontroller:
Microcontroller is employed in Mobile phones, camera circuitry.
Microcontrollers are used extensively in Automobile Industry
Computer Systems like traffic signal controlling.
Different control operation such as heater, greezer, liftcontrol, Micro-oven etc.
Comparison of Microprocessor vs. Microcontroller:
MICROPROCESSOR
MICROCONTROLLER
CPU
It has 1 Central Processing Unit
It has a Central Processing Unit, Memory, Input-output pins.
USE
Microprocessor is used in personal computers.
Microcontroller has applications in embedded system.
INTERFACE
Microprocessor interface is complicated.
Simpler Interface
COST
They are expensive
They are inexpensive
REGISTER
It has less numbers of registers, operations are mostly memory based.
Greater number of registers making it easy for operations.
For more Electronics Articles and question answers related to electronics click here
The 8279, 8259, and 8255 are programmable peripheral devices that play a crucial role in 8085-based microprocessor systems. These devices provide essential functionalities such as data transfer, interrupt management, and keyboard/display interfacing, making them indispensable components in the design and implementation of embedded systems.
8255 Programmable Peripheral Interface (PPI)
The 8255 Programmable Peripheral Interface (PPI) is a versatile, general-purpose programmable device used for data transfer between the processor and I/O devices. It features three programmable I/O ports, designated as PA, PB, and PC, each with a resolution of 8 bits. The 8255 PPI can be programmed to operate in different modes, allowing for flexible and customizable data transfer operations.
Key Features of the 8255 PPI
Programmable I/O Ports: The 8255 PPI has three 8-bit I/O ports (PA, PB, and PC) that can be individually programmed to operate in different modes, such as input, output, or bidirectional.
Flexible Programming Modes: The 8255 PPI can be programmed to operate in one of three modes: Mode 0 (basic input/output), Mode 1 (strobed input/output), and Mode 2 (bidirectional bus).
Interrupt Capability: The 8255 PPI can generate interrupt requests to the processor, allowing for efficient data transfer and synchronization with external devices.
Control Register: The 8255 PPI has a control register that allows for the configuration and control of the I/O ports, including the selection of operating modes and interrupt settings.
Power Consumption: The 8255 PPI has a low power consumption, making it suitable for use in battery-powered or energy-efficient systems.
Programming the 8255 PPI
To program the 8255 PPI, the following steps are typically followed:
Initialize the Control Word: The control word is written to the control register to configure the operating mode, port directions, and interrupt settings.
Set Port Directions: The I/O ports (PA, PB, and PC) are configured as either input or output, depending on the application requirements.
Perform Data Transfer: Data is transferred between the processor and the I/O devices using the configured I/O ports.
Handle Interrupts (if enabled): If the 8255 PPI is configured to generate interrupt requests, the interrupt service routine (ISR) is executed to handle the data transfer or other events.
The 8255 PPI is widely used in 8085-based systems for a variety of applications, such as interfacing with keyboards, displays, sensors, and other peripheral devices.
8259 Programmable Interrupt Controller (PIC)
The 8259 Programmable Interrupt Controller (PIC) is a crucial component in 8085-based systems, responsible for managing and prioritizing interrupt requests from various peripheral devices. It provides a flexible and efficient way to handle interrupts, allowing the processor to focus on its primary tasks without being overwhelmed by constant interrupt handling.
Key Features of the 8259 PIC
Interrupt Request Lines: The 8259 PIC has 8 interrupt request (IRQ) lines, each of which can be connected to a different peripheral device.
Programmable Interrupt Priorities: The 8259 PIC allows for the programming of interrupt priorities, ensuring that critical interrupts are handled first.
Interrupt Masking: The 8259 PIC provides the ability to mask or disable specific interrupt request lines, allowing the processor to focus on the most important tasks.
Interrupt Vectoring: The 8259 PIC generates an interrupt vector, which is used by the processor to jump to the appropriate interrupt service routine (ISR).
Cascading Capability: Multiple 8259 PICs can be cascaded to support a larger number of interrupt request lines, enabling more complex interrupt management in larger systems.
Programmable Operating Modes: The 8259 PIC can be programmed to operate in different modes, such as the 8086 mode, 8080/8085 mode, and special fully nested mode, depending on the system requirements.
Programming the 8259 PIC
To program the 8259 PIC, the following steps are typically followed:
Initialize the Interrupt Controller: The 8259 PIC is initialized by writing the Initialization Command Word (ICW1) to the control register.
Set Interrupt Priorities: The Interrupt Mask Register (IMR) is programmed to set the priorities of the interrupt request lines.
Enable Interrupts: The 8259 PIC is enabled to start accepting and processing interrupt requests.
Handle Interrupt Requests: When an interrupt request is received, the 8259 PIC generates an interrupt vector, which the processor uses to jump to the appropriate interrupt service routine (ISR).
Manage Interrupt Masking: The Interrupt Mask Register (IMR) can be used to mask or unmask specific interrupt request lines as needed.
The 8259 PIC is essential in 8085-based systems, as it allows for efficient and prioritized handling of interrupt requests from various peripheral devices, ensuring that the processor can respond to critical events in a timely manner.
8279 Programmable Keyboard/Display Interface
The 8279 Programmable Keyboard/Display Interface is a specialized device designed to simplify the interfacing of keyboards and displays with 8085-based microprocessor systems. It provides a standardized and programmable way to handle keyboard input and display output, reducing the complexity of the overall system design.
Key Features of the 8279 Programmable Keyboard/Display Interface
Keyboard Interfacing: The 8279 can interface with a variety of keyboard types, including matrix-encoded keyboards, scanned keyboards, and encoded keyboards.
Display Interfacing: The 8279 can interface with various display types, including 7-segment displays, hexadecimal displays, and alphanumeric displays.
Programmable Operating Modes: The 8279 can be programmed to operate in different modes, such as keyboard mode, display mode, and sensor mode, depending on the application requirements.
Interrupt Generation: The 8279 can generate interrupt requests to the processor, allowing for efficient handling of keyboard input and display updates.
Programmable Scan Rates: The 8279 allows for the programming of keyboard and display scan rates, enabling the system to adapt to different input and output devices.
FIFO Buffers: The 8279 includes First-In-First-Out (FIFO) buffers for both keyboard input and display output, allowing for efficient data handling and reducing the burden on the processor.
Programming the 8279 Programmable Keyboard/Display Interface
To program the 8279 Programmable Keyboard/Display Interface, the following steps are typically followed:
Initialize the 8279: The 8279 is initialized by writing the appropriate command words to the control register, configuring the operating mode, scan rates, and other parameters.
Set up Keyboard Interfacing: The keyboard interface is configured by programming the 8279 to handle the specific keyboard type and encoding scheme.
Set up Display Interfacing: The display interface is configured by programming the 8279 to handle the specific display type and output format.
Handle Keyboard Input: When a key is pressed on the keyboard, the 8279 generates an interrupt request, and the processor reads the key data from the FIFO buffer.
Handle Display Output: The processor writes data to the 8279’s display FIFO buffer, and the 8279 updates the connected display accordingly.
The 8279 Programmable Keyboard/Display Interface simplifies the integration of keyboards and displays in 8085-based systems, allowing for efficient and flexible input/output handling.
8085 Microprocessor
The 8085 microprocessor is an 8-bit microprocessor designed and manufactured by Intel. It is a widely used and well-established processor in the field of embedded systems and industrial applications.
Key Features of the 8085 Microprocessor
8-bit Data Bus: The 8085 microprocessor has an 8-bit data bus, allowing it to transfer 8 bits of data at a time.
16-bit Address Bus: The 8085 microprocessor has a 16-bit address bus, which allows it to address up to 64KB of memory.
Instruction Set: The 8085 microprocessor has a comprehensive instruction set, including arithmetic, logical, data transfer, and control instructions.
Interrupt Handling: The 8085 microprocessor supports various interrupt sources, including external interrupts, software interrupts, and hardware interrupts.
Clock Speed: The 8085 microprocessor typically operates at clock speeds ranging from 3 MHz to 6 MHz, depending on the specific implementation.
Power Consumption: The 8085 microprocessor has a relatively low power consumption, making it suitable for use in battery-powered or energy-efficient systems.
Peripheral Interfacing: The 8085 microprocessor can interface with a variety of peripheral devices, such as the 8255 PPI, 8259 PIC, and 8279 Programmable Keyboard/Display Interface, through its I/O ports and control signals.
Programming the 8085 Microprocessor
Programming the 8085 microprocessor typically involves the following steps:
Instruction Set: Familiarize yourself with the 8085 instruction set, which includes arithmetic, logical, data transfer, and control instructions.
Assembly Language: Write programs in 8085 assembly language, which provides a low-level, human-readable representation of the machine code.
Assembler: Use an assembler tool to translate the assembly language program into machine-readable object code that can be executed by the 8085 microprocessor.
Memory and I/O Interfacing: Understand how to interface the 8085 microprocessor with memory and I/O devices, such as the 8255 PPI, 8259 PIC, and 8279 Programmable Keyboard/Display Interface.
Interrupt Handling: Implement interrupt handling routines to respond to external events and manage the flow of execution in the 8085-based system.
Debugging: Use debugging tools, such as emulators and simulators, to test and debug your 8085 programs, ensuring their correct operation.
The 8085 microprocessor is a versatile and widely used processor in the field of embedded systems and industrial applications, and its integration with the 8255 PPI, 8259 PIC, and 8279 Programmable Keyboard/Display Interface provides a powerful and flexible platform for a wide range of applications.
Conclusion
The 8279, 8259, and 8255 programmable peripheral devices, along with the 8085 microprocessor, form a comprehensive and powerful ecosystem for the design and implementation of 8085-based embedded systems. By understanding the key features and programming techniques of these components, electronics students and engineers can develop robust and efficient solutions for a wide range of applications, from industrial automation to consumer electronics.
Solution: 1) It is used in Analog to Digital converters and Digital to analog converters in digital electronics.
36. Mark the given statement as True or false.
Statement: An operation in Flip Flop is faster than an operation in the multiplexer.
True
False
Solution: (2). False
37. Which IC works as a multiplexer?
1) 74HA198
2) 74HC150
3) 74CH199
4) 74HC157
Solution: 4) 74HC157
38. Which IC works as a demultiplexer?
1) 74HC83
2) 74HC38
3) 74CH19
4) 74HC15
Solution: 1) 74HC83
39. Which IC works as Encoder?
1) HT85A
2) HT87B
3) HT12E
4) HT74F
Solution: 3) HT12E
40. What is the lowest no. of OR gate required for the given expression?
Y = A’B + B’A
1) 1
2) 2
3) 4
4) 5
Solution: 1) 1
41. What is the lowest no. of AND gate required for the given expression?
Y = A’B + B’A
1) 1
2) 2
3) 4
4) 5
Solution: 2) 2
42. What is the lowest no. of NAND gates required to make an inverter?
1) 1
2) 2
3) 3
4) 4
Solution: 1) 1
43. What is the lowest no. of NOR gates required to make an OR gate?
1) 1
2) 2
3) 3
4) 4
Solution: 2) 2
44. Which gates are known as universal gates in digital electronics ?
1) OR and AND
2) NOT and XOR
3) NOR and NAND
4) All of them
Solution: 3) NOR and NAND
45. A truth table is given below where A and B are the provided inputs, and from Y the output is taken. Identify the Logic gate.
Digital Electronics MCQ Table – 1
1) XOR
2) NAND
3) XNOR
4) NOR
Solution: 3) XNOR
46. A truth table is given below where A and B are the provided inputs, and from Y the output is taken, for a digital electronics circuitry. Identify the Logic gate.
Digital Electronics MCQ Table – 2
1) XOR
2) NAND
3) XNOR
4) NOR
Solution: 4) NOR
47. Find the odd one out from the digital electronics circuitry.
50. A truth table is given below where A and B are the provided inputs, and from Y the output is taken, for a digital electronics circuitry. Identify the combinational circuit.
Conclusion : With these we are done with the critical Digital Electronics MCQs and To learn more on Digital Electronics Article and Question Answersclick here
Tosca is now become one of the leading test automation tool which follows the script less methodology. Through out the entire Tosca tutorial, we have already learned about the different Tosca components and test automation approach. Now we are going to explain the concepts of API Testing in TOSCA.
In this “API Testing in TOSCA” article, we will explain the overview of API and the detailed steps of automated API Testing in TOSCA.
API Testing in Tosca
What is API?
API is the shorter form of Application Program Interface. It’s working as an interface which allows two applications to communicate with each other through common message formats such as, XML, JSON, etc. Let’s consider the below figure to understand more on API–
Assume, we have four different applications – SAP App, Mobile Apps, Web Portal and Billing System, which are integrated by common interface as API. Here API is working as an interpreter. Each of the system interacting with each other by sending an API request and receiving the API response. Basically, each system is communicating with API and based on the request, API routes the messages to the target system.
API Testing in Tosca – Overview
Purposes of API:
Communicate between different applications.
It’s platform-independent.
Development of one system is not dependant with another.
Fast and secure communication.
Easy to integrate many applications.
Different Types of API:
REST API (Representational State Transfer): It’s a web service API which is now an essential part of modern web-based applications such as, Facebook, Netflix, etc. REST API should comply with below standards –
Stateless – It does not allow to store the data they received from a requestor.
Client-Server Architecture – Client and Server’s REST APIs should be independent with each other.
Cache – The cache is storing the browsing data for a specific period of time.
Uniform Interface – Communication should be HTTP requests using URL, CRUD(Create, Read, Update, Delete) and JSON.
Layered System – REST APIs should use different architecture layers which contributes towards a clear hierarchy.
Code on demand – It’s an optional rule to transmit code within the application through the API.
RPC API (Remote Procedure Call): These are the simplest API which is used from old days. The aim of RPC is to execute code on the server system. It was easier for application developers to develop applications involving more programs or services in the RPC API.
There are two types of RPC APIs – XML-RPC and JSON-RPC.
SOAP API (Simple Object Access Protocol): It is also one kind of web API. SOAP is the first to define the process about the applications to use a network connection to manage services. It’s a special protocol which is defined by the World Wide Web Consortium (W3C).
API Testing in TOSCA:
Before understanding the API Testing in TOSCA, first, we need to understand the “What is API Testing?”.
What is API Testing?
The API Testing is an approach to test the API components of any software product in efficient way. To perform API testing, we need to validate the API response received based on the API request. The main moto of API testing is to test the core functionality, reliability, performance and security through the API. API Testing is ideal for testing the core functionality of the application when the all the application is partially developed. So, it allows us to start the testing before the integration of the software components.
For more information on API Testing, please click here.
API Testing in TOSCA:
The goal of API testing is to ensure that the core functionalities of the application work as expected without interacting in the UI layer. To perform the API Testing, always, we need to take help from any third party tools like Postman, UFT, TOSCA, etc.
Here, TOSCA is one of the best automation tools for API Testing.
Benefits API Testing in TOSCA:
API testing can be used to validate the core functionalities even when the UI hasn’t been developed/modified. Hence testing can be initiated much before actual functional testing (UI based) is done.
Frequent application changes can be tested quickly.
It is easy to maintain test cases in TOSCA.
The API testing in TOSCA can be done much faster.
Standalone Tosca API Scanning Wizard is available to scan the API in the easiest way.
Step2# Identify Scenarios and data formats for the API Request.
Test Scenario – After logging into the sample swagger application, need to add a new coffee brand and verify.
Data Format – Data need to be passed through JSON format.
Step3# Manually Verify the scenario using tools like Postman (Optional). Please go through the article on Postman to understand the process to test the API.
Step4#Scan the API with the endpoint reference. Scanning steps are mentioned below –
1) Open the API Scan wizard from “API Testing” tab available in TOSCA Header section.
2) Click on URI button and enter the endpoint address. Now click on OK to start scanning.
API Testing in Tosca – Scan API
3) After a few moments, API scan will be completed, and scanned API modules are displayed in the API Scan Wizard.
API Testing in Tosca – Scanned Components
Step5# Create modules and test cases – Selecting the root folder, i.e. “Swagger Demo CoffeeShop V2”, click on “API Test Case” to generate modules and test cases in the TOSCA. For every transaction, there are two parts – one for request and another for the response.
API Testing in Tosca – Generated Modules
Step6#Cleanup scenarios: Auto-generated test cases can be used as a base suite which needs to be cleaned by removing the unwanted folders, create module attributes to parametrize the response values such as, authentication token which will be required to perform any transaction.
Post Coffee (Modules for API Request) –
API Testing in Tosca – Modules after Cleanup
After assigning the parameters, the API Test Case will look like below,
API Testing in Tosca – Test Case
Step7# Execute API Test Case in TOSCA – First of all, we need to add the newly created test case into the execution list. Now, the execution can be initiated by clicking on “Run” button. As it’s an API Testing, no application UI will be visible through out the execution. After completion of execution, Report will look like below,
API Testing in Tosca – Execution Log
Conclusion:
In this “API Testing in TOSCA” article, we have learned about API and API Testing in TOSCA. To know more on API testing in Tosca from Tricenties support portal, please click here.
In the microprocessor 8085, accumulator specified as an 8 bit register connected with an ALU. This is utilized to hold one of the operand for arithmetical and logic-operation; it works as input to the ALU. The other operand for arithmetic and logical operation possibly stored either in memory or in GPR. But the final product will be stored in the accumulator only.
8085 microprocessor has 8 bit GPR; it works like a pair – B-C, D-E, H-L
The H-L register pair is used as a memory pointer & it holds 16 bit address of a memory location.
Define Stack Pointer (SP):
Stack pointer is a 16 bit especial purpose register. Stack is a order of memory location set by a programmer. The stack also perform as LIFO (Last in First Out). Here two operations are used; PUSH & POP.
Program Counter Definition:
A 16 bit register for specified operations ; comprises registers to load memory address from wherever the subsequent instruction is to be fetched.
Assume the program counter contains a memory location 7100H, this imply that microprocessor 8085 intended to fetch the instruction at the location 7100H.
Subsequently fetching the 7100H, the program counter is inevitably increses one count. This has the track of memory address of the instruction.
EXAMPLE: JMP, CALL, RETURN, RESTART etc.
Define Instruction Register:
This is an 8 bit register to hold the OPCODE of the instructions that has to be decode and execute. This is not accessible to the program writer.
Define Temporary Register:
This is a 8 bit non-programmable register utilized to keep data through an arithmetic and logical instruction implementation. TR is keeping intermediate results only and ultimate finalized end result is saved in the accumulator. This is microprocessor dependendent, not controlled by developer code.
Addressing Modes of Microprocessor 8085:
What is Addressing Mode?
“Addressing mode is the best way to define a certain data to be controlled by means of an instruction.”
Microprocessor has various kinds of addressing mode as it gives flexibility to the developer to get info and acessing data.
What are the types of Addressing Mode?
There are total five category as follows:
The Direct Mode
The Register Mode
The Immediate Mode
The Register Indirect Mode
The Implicit Indirect Mode
Direct Addressing Mode (DAM):
In this mode the address of the operand is identified the instruction the aforementioned. Instruction that includes direct address require 3-bytes of storage space of Microprocessor 8085.
Instruction Code
16 Bit Address
Sample instruction like STA 2500H stores the content of the accumulator in the memory location noted 2500H. Here 2500H is the address located in memory space where data is has be kept in.
Register Addressing Mode:
Here the operands are GPR. The opcode identifies the address of the register in addition to the operation to be executed.
For example the instruction MOV A, B will move the data of register B to register A. In other instruction like ADD B, A; will first doaddition operation with the data of register B to register A and the end result is to be stored in register A.
Immediate Addressing Mode:
Here the operands are specified within the instruction itself, that means when any data has to be performed then immediately the operation is executed.
Example – MVI 05
ADI 05
Register indirect Addressing Mode:
In this case the operand will be identified by the register-pairs. Here accumulation is not linked directly.
Example are H-L, B-C, D-E etc.
Implicit Addressing Mode:
There are certain instructions which operates on the content of operator. These instructions will not call for address of operand.
Example – JMP, CALL, RAR
Timing Effects of Addressing Modes:
Addressing modes influence both the quantity of time necessary for executing an instruction and the total amount of memory necessary for storing. By way of instance, instructions which use suggested or register fixing, execute quickly because they deal directly with the chip hardware or with information present in hardware registers.
Most significant, however instruction can be fetched using one memory access. The Amount of memory accesses necessary is the factor in determining performance time, more memory accesses thus require more implementation time.
For example, to executing a CALL instruction requires 5 memory entrees; out of these 3 will be for the access the entire instruction and the 2 will be for PUSHing the contents of the program counter onto the stack location.
The processor can access memory during every processing cycle. Each cycle includes a varying number of states. This is dependent upon the clk freq, and which might vary from 480 nSec to 2µsec. The 8085 have clk freq around 5 MHz and so a minimal state may be of 200 nanosec.
What is Subroutine?
Creating a program of specific operation may happen several occasions and they’re not accessible as individual directions along with the application for such operation replicated over and over. However, the program ought to be written. The idea of subroutine is used to prevent the repetition of this smaller coding. The little program for specified for small job is called subroutine.
Subroutines are composed individually then saved to the primary memory by utilizing RET. CALL instruction is generally utilized from the primary memory to subroutine.
Instruction Cycle of Microprocessor 8085:
This is the time taken by the microprocessor to finish the execution of the instruction. An instruction cycle usually consists of 1 to 6 machine cycles.
Machine Cycle
It is the time prerequisite to finish an operation through access one or the other the memory or I/O devices. It consists 3-6 T states. Here, opcode fetch, memory read, memory write, I/O read-write, operation executed. In the other word the operation of retrieving either memory devices or I/O devices is termed machine cycle.
T State:
This is the time equivalent to the one clock period in the basic unit used to calculate the time taken for the execution of the instruction and program in the microprocessor.
Fetch Operation:
The very initial byte of an instructionset is the OPCODE. An instruction usually more than 1 byte length. Another byte is for information data or for the operand address. At the start of the cycle that the info of program counter where opcode can be obtained is forwarded to the memory. This required 3 clock cycle another one is undefined.
What is the difference between CALL & JMP instructions of of Microprocessor 8085?
After a jump instruction is performed, the address given in JMP instruction is moved to PC. Thus application control is automatically progressed to this place location and carrying out as continued execution.
When CALL instruction is completed, microprocessor first keep PC info in the stack. Subsequently PC is occupied with the address set in the CALL instruction.Hence program control will transfer there.
What is Conditional & unconditional JUMP?
The JUMP commands are two kinds, specifically ‘unconditional jump’ and ‘conditional jump’. If the microprocessor is indeed initiated to load a new address in the PC and commence instructions in that, it’s termed as an unconditional jump. In the instance of a conditional jump, the PC is loaded with a new address only when certain conditions are created from the microprocessor after reading the correct status of register bits.
Testing is now an essential phase of the software development life cycle to secure the product’s quality. Also, without having testing, we can’t ensure the fulfillment of all the requirements. Here automation is playing an essential role in the testing cycle to reduce the efforts and time. In the market, there are multiple testing tools available to automate the testing process. The most used automation testing tool is UFT.
In this UFT Tutorial, we are going to learn the below topics –
Automation recording in uft is an option to record the manual navigation in the test application through the UFT tool to generate the linear test scripts. All the data in the recoded scripts are hardcoded. The record and play approach is ideal for one-time execution. But for the longer run, we need to modify the recoded test cases to implement data parameters, reusables proper test framework, etc. Recording in UFT can be initiated by pressing the F6 key or Record button under the Record tab.
Limitations of recording in UFT:
· All the data are hardcoded.
· Recorded scripts are not stable and difficult to use for the longer run.
· Required high maintenance efforts.
· Redandant duplicate object hierarchy can be created.
Different options for recording in UFT:
· Normal mode/ UI Automation Recording – It’s also known as Contextual, which is the default recording behavior that uses the full features of the UFT object recognization approach. It’s used to record UFT compatible applications.
· Low-level recording mode – If the application is not compatible with UFT, i.e., the entire screen is identified as a single Win Object. In this case, the low-level recording mode can be used to record the steps based on the application co-ordinates.
· Analog Recording – It’s used to record mouse movements and keyboard operation.
· Insight Recording – Insight objects can be inserted on any AUT. Once we press the Record button, Insight Recording appears under the Record menu and recording toolbar.
Different recording options can be chosen by selecting the recording mode from the recording wizard.
Recording in UFT – Types
Step by step Guide for Recording in UFT:
Recording Scenario: Search the keywords “Automation Testing” on google.
Step1# Open internet explorer and navigate to www.google.com.
Step2# Start the recording by pressing the “F6” button or selecting the menu “Recording-> Record F6”.
Recording in UFT – Step2
Step3# For the first time below “Record and Run Settings” wizard appears to configure the recording settings such as URL, Record, and run on any open browser, etc. Same configurations are also available for mobile or Windows Applications. Here, we will select the “Record and run on any open browser” option and proceed.
Recording in UFT – Step3
Step4# Now the recording wizard appears, and we can manually navigate the scenario in the web browser. UFT will capture the steps which are performed manually and store in the test case.
Step5# After completion of manual navigation, click on the stop button to end the recording. The recorded script will look like below.
Recording in UFT – Step5
Checkpoints in UFT:
Checkpoints in UFT are used to verify the specified properties of objects between actual values and expected values. These verification points are performed at the run time. If the expected values are matched with actual, UFT will generate PASS statue; else, it will be FAIL status. Checkpoints are used based on functional specifications.
Types of Checkpoints in UFT:
There are different types of checkpoints available in UFT. Those are –
· Standard checkpoints in UFT: It validates the expected values of the object, which are captured during recording with the actual values of the object during the execution time.
· Page Checkpoints in UFT: When a standard checkpoint is created for a web page is called a page checkpoint. Page checkpoints in UFT are used to validate the different types of object count, such as links, images, etc. Also, it can be used to check the time taken to load the web page.
· Bitmap Checkpoints in UFT: It is used to check the bitmap of an image or the entire webpage. It performs a pixel to pixel comparison of the test image.
· Image Checkpoints in UFT: It helps us to check properties like the source file of the image. We can not use it to check the bitmap or pixel of the images.
· Text Checkpoints in UFT: It checks the text available in a webpage or application. This text can be available in a small portion or section of the application.
· Accessibility Checkpoints in UFT: It verifies standards as per W3C instructions and guidelines for Web-based technology and information systems.
· Database Checkpoints in UFT: It’s used to verify the database. It creates a query to store database values as expected values during recording time. During the execution, the same query is used to capture current values from the database, which will be compared with expected values.
· Table Checkpoints in UFT: In Table Checkpoint, we can check the contents of the table during the run time. Initially, these checkpoints store the contents of a table as an expected value, which will be verified with the actual table value during execution.
· XML Checkpoints in UFT: It’s used to verify XML files.
Step by Step Guide to Create Checkpoints in UFT:
Now, we will learn how to create standard checkpoints in UFT based on the below example. By following the same guide, we can create different types of checkpoints.
Checkpoint Scenario: Create standard checkpoints in UFT during the recording in the web-browser.
Step1# Open internet explorer and navigate to www.google.com.
Step2# Start the recording by pressing the “F6” button or selecting the menu “Recording-> Record F6”.
Step3# Search the keywords “Automation Testing” on google to record the corresponding automated scripts.
Step4# Now select Standard checkpoint from the menu navigation “Design->Checkpoint->Standard Checkpoint F12” or pressing the “F12” key.
Checkpoints in UFT – Step4
Step5# Select the desired object in the application for which a standard checkpoint needs to be created. Here, we are selecting the web element to verify the text “Test Automation Software.”
Checkpoints in UFT – Step5
Step6# Review the Checkpoint properties and click OK to add the checkpoint step into the test case.
Checkpoints in UFT – Step6
Step7# Checkpoint step is now added in the script. Also, the same is available in the object repository as well. In this scenario, the inner text property of the test object will be validated during the execution.
Checkpoints in UFT – Step7
Step8# Checkpoint verification status can be seen in the UFT execution report.
Checkpoints in UFT – Step8
Dictionary Object in UFT:
The dictionary object in UFT is similar to the array. But the primary difference with the array is that there is a key associated with each element in the dictionary object.
The dictionary object in UFT can be defined by referring to the Scripting.Dictionary class.
Advantages of Dictionary Object in UFT:
· It stores items in an organized way.
· Easy to access any items using the key string.
· It is more flexible to handle with pre-defined methods.
Example of Dictionary Object in UFT:
Create a Dictionary Object:
Dim dict’ Create a variable.
Set dict = CreateObject(“Scripting.Dictionary”)
dict.Add “Company”, “Microfocus” ‘Adding keys and items.
dict.Add “Tool”, “UFT”
dict.Add “Trainer”, “LambdaGeeks”
Checking the Existence of Specific Keys:
If dict.Exists(“Company”) Then
msg = “Key exists”
Else
msg = “key doesn’t exist”
End If
Read Any Item: dict.Item(“Company”)
Get The Count: dict.count
Delete Any Item: dict.Remove(“Company”)
Delete All Item: dict.RemoveAll
Test Execution in UFT:
Steps for Test Execution in UFT are shown below –
Step1# Open the test case in UFT.
Step2# Click on the Run button or press the “F5” key to initiate test execution in UFT.
Step3# Now, we need to select the Result Location. If there are any ALM test sets are available or need to execute from a specific folder, we need to select the first option, i.e., “New run result folder.” For any temporary run to check the script, we need to select the second option. Once the selection is done, please click on the Run button to start the execution.
Test Execution in UFT – Run Setting
Step4# After completion of the execution, we can view the default UFT result from the menu navigation “View->Last Run Result.”
Test Debugging options in UFT:
The different debugging options are mentioned below –
Debug Point: By pressing on the “F9” key, the debug point can be added to the selected line of code. It’s required to pause the execution pointer at this particular line. Using the same key, we can also remove the selected breakpoint.
Run From Step: By pressing on the “Ctrl+F5” keys, execution can be started from the selected step.
Step Over (F10): If we want to perform line-by-line debugging, we need to keep on clicking on the “F10” key.
Step Into (F11): If we want to perform line by line execution, including child components as well, we need to keep on pressing the key “F11”.
Clear All Breakpoints: We need to press on keys “Ctrl+Shify+F9”.
Conclusion:
In this “Advance UFT Features” article, we have learned about important advanced UFT concepts such as Recording, Checkpoint, Dictionary Object, Test Execution in UFT, etc. Click here to understand more from the Microfocus support
portal. Also, if you want to prepare for UFT Interview Questions, please click here.
Masking can be implemented for the 4 hardware interrupts- RST 7.5, RST 6.5, RST 5.5 & INTR. In this figure, TRAP is NMI (Non Maskable Interrupt).
RST 7.5 alone has a F/F to recognise its edge transmission. The masking of interrupt can be done using SIM instruction. In additional a separate interrupt enables F/F is available to mask or allow the interrupts.
The maskable interrupts are masked by default by means of the reset signal.
The interrupt can be enabled by execution of EI instruction. So, to enable interrupts, after resulting the microprocessor the EI instruction must be used in 8085 microprocessor.
The 3 RST interrupts could be masked by load up the suitable word variety in the accumulation and implementing SIM instruction. This is known as software-masking.
All the maskable interrupts are disabled whenever an interrupt is recognized. So, it is essential to perform EI instruction every single time.
Altogether, the maskable interrupts may be disabled by performing DI instructions. The instruction resets an interrupt enable F/F in the microprocessor. For the enabling purpose, instruction EI is utilized.
TRAP:
It is non-maskable interrupt such that it need not to be enabled and cannot be enabled or disabled.
It is accessible to user
It is used for emergency situation such as power failure or energy shut off etc.
It is edged as well as level triggered that is the i/p should goes high and stay in this condition to acknowledgement.
TRAP has highest priority amongst all.
RST 7.5:
Its priority is just after the TRAP.
It is maskable such that both EI and DI operation can be possible.
It is sued for the situation whose priority is just after emergency situation.
It is positive edge triggered interrupt.
It can be triggered with a very short duration pulse.
RST 6.5:
Its priority is just after RST 7.5.
Other specifications are as same as RST 7.5.
RST 5.5:
Its priority is just after RST 6.5.
Other specifications are as same as RST 7.5.
INTR:
INTR is the lowest priority interrupt.
This is edge as well as level triggered.
Maskable and non-vectored type.
Both EI and DI can be possible in this situation.
Operation of INTR:
The signal flow sequence is as follows to INTR goes high.
8085 authorizations the status of the INTR, for carrying out an instruction.
If INTR signal is 1, then 8085 will complete its present instruction and an active-low interrupt will be acknowledged by an interrupt ACK.
Then the address of next instruction will be loaded in stack and will perform received instruction.
INTA:
It is not the interrupt just used by the microprocessor sent the acknowledgement. The process should be enabled by instruction.
During T3 condition of the opcode fetch, 8085 checks repeatedly of every instruction. If interrupt finds the microprocessor will complete execution instruction and ready for the restart sequence.
The restart sequence resets the interrupt F/F and active INTA upon receiving the signal.
Interrupt Call Locations:
The call locations for 8085 are
TRAP- 0024
RST 7.5- 003C
RST 6.5- 0034
RST 5.5- 002C
SIM Operation (Set Interrupt Mask):
SIM (Set Interrupt Mask) for 8085 is explained as follows
M 5.5 – it is basically set to 1 to reset 5.5 mask
M 6.5 – it is also set to 1 to reset 6.5 mask
M 7.5 – it is also set to 1 to reset 7.5 mask
MSE – to mask interrupt
R 7.5 – it is reset RST 7.5 F/F
SDE – serial data enable set to 1 for sending
SOD – serial output data to be sent
EXPLANATION:
RST 7.5, 6.5 & 5.5 are maskable interrupts. The instruction EI and SIM utilized for enabling these.
BIT 0 to 2 is either set or reset the mask for RST 6.5, 7.5 & 5.5.
If a bit is set to 1, then the interrupt is masked off i.e., disable. If set as 0, the respective interrupt is enabled.
If bit 3 is set to 1 to mask on bit 0 to 2.
BIT 4 is additional control for RST 7.5. If it is set to 1 the RST 7.5 is reset.
Bit 6 and 7 are serial output data where bit 6 is to enable SOD and bit 7 may be either high or low. The instruction DI disable all the interrupts.
PENDING REQUEST:
When 1 interrupt request is being served, other interrupts may occur resulting in pending request. When more than 1 interrupt occur simultaneously then interrupt having higher priority has served and interrupt having lower priority remain in the pending condition.
8085 microprocessor has an additional instruction called RIM (Read Interrupt Mask) to sense the pending interrupt.
RIM Operation (Reset Interrupt Mask):
RIM (Read Interrupt Mask) for 8085 is explained as follows
M 5.5: This bit is set to 1 if RST 5.5 is masked. The bit 0 to 2 could be used for interrupt mask utilizing RIM instruction
M 6.5: This bit is set to 1 if RST 6.5 is masked.
M 7.5: This bit is set to 1 if RST 7.5 is masked.
IE: It is set to 1 if all interrupts are enabled.
I 5.5: It is set to 1 when RST 5.5 is in pending condition.
I 6.5: It is set to 1 when RST 6.5 is in pending condition.
I 7.5: It is set to 1 when RST 7.5 is in pending condition.
SID: Serial Input Data; it will be either 1 or 0 for input purpose.
Vectored Interrupts:
TRAP, RST 7.5, RST 6.5, RST 5.5 (call location).
SOFTWARE INTERRUPTS VS HARDWARE INTERRUPT:
Software Interrupts
This are the software instructions when they are executed, CPU branches to ISR.
These are slower than the hardware interrupts.
Examples – RST 0, RST 1, RST 2 etc.
Hardware Interrupts
These are physical input from external devices which causes CPU to branch to ISR.
These are faster than software interrupts.
Examples – TRAP, RST 7.5 etc.
What is Stack?
Stack
A stack in 8085 microprocessor is a set of memory location in read-write memory specified by a programmer in a main program. These memory locations are utilized to store binary data momentarily during coding.
The initiation of the stack is defined in the program by executing the basic load instruction such as LXI SP. This generally load a sixteen bit memory address in the SP register.
Types of Stack:
PUSH
POP
PUSH – In the course of execution, PUSH is required to resolve the problem of certain register since the registers are prerequisite for some additional execution in consequent state. These contents move to certain memory location by a special function register is called PUSH.
Example-
LXI SP, 2099 H
LXI H, 42F2 H
PUSH H
Loads the contents of 2099H with SP register that is reserved in read-write memory as a state and the location begins from 2098H in moving upward for temporary storage.
LXI H, 42F2H describes the loading of H-L pair i.e., (42) is loaded in H and F2 is loaded in L.
PUSH H indicates that the content of H i.e., 42 stored in 2098H and the content of L i.e., F2 is stored in 2097 H.
POP – After completion of this operation this content which are saved in the temporary register are transferred back to the main memory by the operation of POP.
Example –
LXI SP, 2099 H
LXI H, 42F2 H
PUSH H
DELAY COUNTER
POP H
The contents of register H-L pair are not destroyed. It is available of the delay counter in the content of the program counter. The content of the top stack location shown by SP appear into the register L and SP will increase 1.
The content of top of stack i.e., 2097 is shifted to 2098 and 2099 by 1 incarnated and from the temporary register the contents move to the main register.
It has inputs for each of the octal digits that is a total of eight in number. It has three output lines (according to the rule that the 2n input line encoder will have n output line). The outputs represent the numbers in binary.
The encoder can be implemented using OR gates. Output C is equal to 1 if the octal digit’s value is 1, 3, 5, 7. The output B will be one if the octal number has a value of 2, 3, 6, 7. The output AS will be one if the input octal digits’ value is 4, 5, 6, 7. The following Boolean expressions represent the outputs.
A = O4 + O5 + O6 + O7
B = O2 + O3 + O4 + O7
C = O1 + O3 + O6 + O7
O0
O1
O2
O3
O4
O5
O6
O7
A
B
C
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Octal to Binary Encoder Truth Table
The encoder implemented at the table has the only limitation. That is, only one input can be in active mode at any given time. That is why if two inputs are made active, then the output lines produce undefined outputs.
Let us take an example if the input O3 is in an active state as well as input O6 is also in an active state, then the encoder produces output as 111. The result neither represent O6 nor O3. So, there is a mess.
To solve this problem, new encoders are designed with an input priority to make sure that only one input gets enabled at a time. If priority is set high for higher digits in this new system, then for enabled O3 and O6, the output will be 110, representing 6 in binary. This happens as O6 has a higher priority than O3.
Priority Encoder
A priority encoder is a particular type of encoder circuit which has a priority function for the inputs. The priority function works in the real world. For example, if there is a queue and you have a high priority, you go first! If there is an operation where both the input values are 1, then the 1 with the highest priority will take precedence.
O0
O1
O2
O3
A
B
Y
0
0
0
0
X
X
0
1
0
0
0
0
0
1
X
1
0
0
0
1
1
X
X
1
0
1
0
1
X
X
X
1
1
1
1
Truth Table for Priority Encoder
As we can see from the truth table of the priority encoder, it has three outputs. Two are general outputs; another one, Y, is a valid bit indicator.
The right bit indicator is set to 1 when one or more than one input has a value of 1. If there are such conditions, where all inputs are set to 0 or the information is not valid, then Y also becomes 0. There is no checking of other outputs if the Y term is 0.
Then, they are specified as don’t-care terms. Truth tables use don’t-care words to represent 0 or 1 rather than listing up 16 terms for variables. For example, 100X means either 1000 or 1001.
As mentioned earlier, the higher the subscript number, the priority of the number gets high. From the truth table, we can see that input O3 has the highest priority as the input. That is why whatever the values for other input digits when the O3 value is 1, the output becomes 11. Similarly, O2 has a priority lower than O3 and higher than O1 and O0. When the input of O2 is 1, the result will be 10. In the same way, for O1, the output is 01, and for O0, the outcome will be 00.
The Boolean function for the priority encoder will be:
How does a priority encoder circuit differ from multiplexer? Read Here!
DECODERS
Definition and Overview
A decoder is a combinational circuit that does the opposite operation of an encoder circuit. It decodes or simplifies the encoded information from n input lines to a maximum of 2n output lines.
Binary codes represent information of distinct quantities. An n bit binary code can represent a maximum of 2n different elements of encoded data. A decoder decodes that information and provides the output.
Decoders are specified as numbers of input to numbers of output line decoders. If the number of input lines is n, then there will be a maximum of 2n output. Every single input combination produces a distinct output value.
To illustrate the working of a decoder, let us take the example of a 3:8 decoder. The specification suggests that the circuit will decode the three input lines into eight outputs of every single output represents the min-terms. The connected NOT gates inverts the input data lines whenever necessary. The AND gates (total eight in number) produces the min-terms (each for one output).
A
B
C
O0
O1
O2
O3
O4
O5
O6
O7
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
Decoder Truth table
From the truth table, we can observe that seven outputs have a value of 0 and one output, which have a value of 1. The outcome, which has a value of 1, represents the actual input value or the min-term.
There are decoders that are constructed with universal basic gates like NAND and NOR. Using a NAND gate is economical as well as efficient to build a decoder. Decoders also need to enable inputs like encoders. The decoder gets enabled when the enable input pin has a value of 0. Only one output may have a value of 0 at a time, and the rest of the outputs will be equal to 1. The truth table below simplifies the operation.
Enable
A
B
O0
O1
O2
O3
1
X
X
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
1
The circuits get disabled if the E value is set to 1. Like the encoder circuit, if the E value is set to 1, there will be no checking of other inputs. In the disabled state of the decoder, no outputs have the value 0, and no min-term is elected. Many decoders have more than one enables pin. They need to abide by the logical operations to perform as a decoder.
A demultiplexer can be made using a decoder if the decoder is added with enable inputs. Parallelly corresponding decoders can make large decoders.
Implementation of logic using decoders
A decoder has 2n input data lines and n output lines. 2n represents the minterms, and n represents the number of variables using which the minterms are formed. As mentioned earlier, for each combination of inputs, there are different outputs.
A decoder can be used to implement logic gates as Boolean functions are nothing but the sum of minterms. An OR gate connected with a decoder can implement the logic of a Boolean function.
Decoder with an enable
Applications of Encoders and Decoders
Encoder circuit and decoder circuit have applications in smart digital devices as they are significant for today’s’ digital era.
Some of the significant applications are –
Speed Control of modern motors.
Night vision cameras
Metal detectors
encoder circuit has applications in Robotic vehicles
Automation system – especially the home automation system.
Automatic Monitoring systems has different types of encoder circuits.
Encoder circuit has utilized in encrypted communications system.
