8279, 8259 PIC, 8255 PPI of 8085 Microprocessor: 3 Facts

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CONTENTS

  • 8279 – The Keyboard and Display Controller
  • 8259 – PIC- The Programmable Interrupt Controller
  • 8255 – PPI- The Programmable Peripheral Interface

8279 – KEYBOARD & DISPLAY CONTROLLER:

PIN Diagram of 8279:

PIN Diagram of 8279
PIN Diagram of 8279

Uses of Different Pins in 8279:

DB0 – DB7 –

Pin no 19: Bidirectional Data Bus; all the data and commands between CU and 8279 are transmitted on this line.

CLK –

This is used to produce internal timing signal for 8279.

RESET –

Pin 9: after being reset, 8279 is placed into the following mode-

  1. 16, 8-bit character display
  2. Embedded scan keyboard.

CS –

A low in this pin enables the interfacing function to receive or transmit for 8279 chip.

A0 (Pin no 21) –

Buffer address, in indicates the signal in or out. In or out operation is taken as command or status.

RD (Pin no 21) & WR (Pin no 10) –

This is for Enabling the data buffer to either sending data to the external bus or receiving the data.

IRQ (Pin no 4) –

This is for the Interrupt request operation in 8279; the interrupt line high when there is a data is in the FIFO.

SL0 – SL3 (Pin no 32-35) –

These are employed as to scan the key switchs, sensor matrix and the display digits. These lines has to be either encoded or decoded as per utilization.

SHIFT (Pin no 36) –

The SHIFT I/O status is put in storage alongside key positions in the scan keyboard operation. Shift pin is an active internal draw to halt high until a switch closer tweak it to low.

BD (Pin 23) –

This pin is for Blank display; this is utilized to blank the display digit via command.

CNTL/STB (Pin 37) –

This is for the Control I/P mode for keyboard operation, employed as a control I/P and stored keystatus. The line work as strobe line which enters the data in the FIFO during the strobe I/O operation.

OUT A0 – A3 (pin 24-27) & OUT B0 – B3 (pin 28-31) –

These are the display pins. These two ports are O/P for 16X4 display refresh register. The data’s from these O/Ps are synchronized to the specified scanned lines SL0 – SL3 for multiplexed digital display. The two 4 bit port may be balanced independently. So a total of 8 bit will be balanced.

What are the two key lockout and N-key rollover mode in 8279?

In 8279, when the I/O mode is programmed to be scanned keyboard mode, then two keyboard modes two key lockout and N-key rollover modes are applied.

What is Scan Keyboard Mode?

When a key is processed, then the debounced logic is in operation. During the subsequent two scans, other keys are assessed to get a closer, and when no different key is pressed, the 1st key is identified and entered into the FIFO. When the first key is released prior to others pushed with two scans, then the 1st key is ignored. When two keys are pressed within a debounce cycle, then no key is recognized until one of these is released while the other stays closed. In that scenario, the previous key that remains pressed is returned to the FIFO.

N-Key Rollover Mode:

Each essential depression is handled independently. When a key is pushed, the debounce logic waits for 2 tests and checks if the key remains pressed or not, for true case, it’s returned into FIFO. In this manner, number of keys could be pressed ; all of the keys have been returned into FIFO in the sequence they had been pressed.

8259 – Programmable Interrupt Controller (PIC)

PIN Diagram of 8259:

2 1
PIN Diagram of 8259, Image Credit – German, Intel 8259, CC BY-SA 3.0

Features of 8259 PIC:

  • The 8259 has total 28 pin.
  • This is a PIC controller.
  • The 8259 capable to handle upto 8 vector priority interrupts for CPU.
  • The 8259 utilizes NMOS & have need of  +5V dc power supply.

Pin Descriptions of 8259 PIC:

  1. CS – when chip select pin is low, it enables RD & WR operation in the CPU & 8259
  2. RD – a low signal allows 8259 to send command of a various status signal on the data bus for CPU.
  3. WR – low WR enables 8259 to accept command word from CPU.
  4. D0 – D7 – bidirectional data bus controller. The control status and interrupt vector information are transferred through this bus.
  5. CAS0 – CAS2 (cascade lines): 8259 has 8 interrupts when no. of interrupt requirement is more, multiple interrupt controller must be connected in cascade. The CAS lines are used to control a multiple 8259 structure. These pins are O/P for master 8259 & i/p for a slave 8259.
  6. SP/EN: slave program/enable buffer – dual when 8259 is used in the buffered mode, it can be used on an o/p to control buffer. If not in buffer mode, it is used to designate a master (SP=1) or (SP=0).
  7. A0 = address line with RD, WR, CS
  8. INT – It goes high when a validated interrupt request is apeared, INT generally used to interrupt the CPU.
  9. INTA – This goes high when a validated interrupt request is associated, used to enable 8259 interrupt vectors onto the databus by a sequence of interrupt ack trigger pulse.
  10. IR0 – IR7 – each pin can be used to receive an interrupt request to the CPU.

8255 Programmable Peripheral Interface (PPI):

PIN Diagram of 8255:

3 1
PIN Diagram of 8255, Image Credit – Miguel Durán, 8255, CC BY-SA 2.5

A PPI is a special multi-port device. The ports may be programmed in various ways as per utilization. These could be employed for interfacing also.

  • Its main tasks are to interface peripheral devices to the processor.
  • 8255 equiped with three 8-bit ports. Port A, Port B and Port C.
  • The Port- C is divided into two 4-bit ports. Port c upper & port C lower.
  • So, a total of 4 ports are available two 8-bit ports and two 4-bit ports are available.
  • These all ports may be programmed utilizing either by I/P port or an O/P port.

Characteristics  of 8255

  • 40 pin IC package.
  • +5V power supply
  • Temperature range 0˚ – 70˚
  • The voltage on any pin is 0.5 V – 7 V.

Pin description of 8255 PPI:

  1. CS – This is the Chip selection signal; CS is the active low signal, means this signal enables communication within CPU with 8255 when active low.
  2. RD –RD is the active low signal;So if RD goes low, 8255  will transfer output datas or status information to the CPU via data bus, or it permits the CPU reading operation from the I/P port of 8255
  3. WR – The WR must goes low, the CPU writes control words or datas with the help of 8255 PPI.
  4. A0 – A7 – the selection of I/P port & controlled word register is made by using these pins with the help of RD & WR.
  5. Port controlled word register –
4 1
for 8255.1
5 1
for 8255.2

If we write the instruction in 00, it means it is for port A of 8255.1. during the instruction implementation, then data  will go port A to the accumulator space.

The instruction OUT 03 will transfer the content of the accumulator of the 8255.1.

  • D0 – D7 – bi-directional data are transmitted or received by the button upon execution of i/p or o/p instruction by the microprocessor. Control and status info is communicated through data bus buffer.

Operating Modes of 8255 PPI:

It has basic three operating modes –

  • Mode 0: Simple I/P 7 O/P
  • Mode 1: Stopped I/P & O/P
  • Mode 2: Bi-directional Port

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