8086 Microprocessor | PIN Diagram | It’s Architecture and important Addressing Modes

CONTENTS

  • Intel 8086
  • PIN diagram
  • Different addressing modes
  • Different Flags Register
  • Pipeline architecture in 8086 microprocessor
  • Advantage of pipelining
  • Memory segmentation in 8086
  • Difference between 8085 and 8086 microprocessor

What is Microprocessor 8086?

8086 microprocessor
Image Credit :Thomas NguyenIntel C8086CC BY-SA 4.0

INTEL 8086:

  • Microprocessor 8086 first invented by INTEL in 1976.
  • 8086 is equipped with 16-bit, HMOS N-channel based microprocessor.
  • This has two modes; minimum and maximum.
  • 8086 has total twenty (20) address lines
  • 8086 has sixteen (16) data lines.

PIN diagram of 8086 microprocessor:

8086 Microprocessor
8086 Microprocessor. Image Credit; Unknown authorUnknown author, Wyprowadzenie mikroprocesora 8086, marked as public domain, more details on Wikimedia Commons

What is Addressing Mode?

“Addressing mode is the way to specify a particular data to be operated by an instruction.”

We need different types of addressing mode because it provides flexibility to the programmer to access data.

What are the types of Addressing Mode in 8086?

The different types of Addressing Modes are explained below:

Register Addressing: 

The operand is a register.

                                     Example – MOV, AX, BX

Immediate Addressing:

The instruction itself comprises the operands.

                                     Example – MOV, AX, 5000H

Direct Addressing:

The instruction specifies the address the operand.

                                    Example – MOV, AX, 9000H

Indexed Addressing:

The operand is specified using one of SI and DI as index register, along with an optional offset. The address of operand is acquired by addition of the information of the index register with the offset, if present.

                                      Example – MOV AX, [SI] or MOV AX, [SI+1000H]

Based Addressing:

The operand is specified using one of BX and BP as base register, along with an optional offset. The address of operand is acquired by addition of the information of base register with the offset, if present.

                                     Example – MOV AX, [BX] or MOV AX, [BP+1000H]

Based-Indexed Addressing:

The operand is specified using one of SI and DI as index register and ones of BX and BP as base register, along with an optional offset. The address of the operand is acquired by addition of information of the index register with the contents of the base register and the offset, if present.

                                    Example – MOV AX, [SI+BX] or MOV AX, [DI+BP+1000H]

Different Flags in 8086 Microprocessor:

  1. S (Sign Flag) – Set when answer of computation is negative.
  2. Z (Zero) – Set when computation of previous instruction is zero.
  3. P (Parity) – Set when lower byte contains even number of ones.
  4. C (Carry) – When there have carry in computation.
  5. T (Trap) – when processor enters single step instruction mode.
  6. I (Interrupt) – Maskable interrupts are identified.
  7. D (Direction) – In string manipulation.
  8. AC (Auxiliary Carry)
  9. O (Overflow) – When result is larger to accommodate in registers.
Register Flag

Pipeline Architecture in 8086 Microprocessor:

The fundamental idea of pipelined architecture is to sub divide the processing of a computer instructions into a series of independent stage (like “pre-fetch”, “fetch”, “decode”, “execute” etc.) with storage at the end of each step.

This permits the computer’s control to instruct the processing speed of the slowest step that is a lot quicker than the time requirement to do all steps at the same time. The pipeline signifies how every step is taking information simultaneously, and any step is linked to subsequent one.

In this, there are 2 separate units

– The “Bus Interface Unit” (BIU)

–  The “Execution Unit” (EU).

The BIU executes all bus operations for the execution unit. The data is in communication in between the CPU and memories and input output kit upon request from the EU. During this if the EU is active implementing commands, the BIU “look ahead” and brings more instruction from the memory. This way, a type of “Fetch-Execute-Pipeline” is implemented in 8086.

Write down some of the Advantages and Disadvantages of Pipelining?

The advantages of pipelining are:

• The cycle time of the chip is comparatively lesser. Pipelining does not minimize the time necessary to finish an instruction; rather it raises the quantity of instructions which may be processed concurrently and reduces the delay between complete instructions.

• The multiple no increased pipeline stages means that more commands could be processed at once and the less delay in between the commands. Every overriding simulated microprocessor manufactured today uses at least two stage pipelines around 30- 40 stages.

• When pipelining is employed, the CPU ALU designed to work fast, but with more complicated design.

• Pipelining in concept improves the performance within an un-pipelined core by a factor stage no and also the code is impeccable for pipeline implementation.

•Pipelined CPUs in general work at a much higher clock frequency than the RAM and that improves overall processor performances.

The disadvantages of pipelining are:

  • This is a non-pipelined chip, simpler in design and more economical to fabricate, implements just a single instruction at a time. This avoids when sequential instructions being executed simultaneously.
  • This type of processor have more instruction latency in comparison to some non-pipelining chip. The operation of a pipelined processor is a lot more difficult to predict and might vary widely for various applications.

What are the functions of BIU and EU 8086 microprocessor?

Define Execution Unit (EU):

The execution unit of the 8086 and 8088 are indistinguishable. A 16-bit ALU in the EU keep up the CPU status and control flag, and deploys the general registers and instruction operand etc. All registers and datapaths from the EU are all 16 bits length for internal communications.

The EU does not have any link to the machine BUS, the external world. This acquires directions from the BIU via queue. Similarly, as soon as an instruction needs accessing memory or peripherals, the EU asks the BIU to access or to keep the information. The BIU, however, relocate address to provides the EU entry to the entire storage.

Define Bus Interface Unit (BIU):

The BIUs are employed differently to match the arrangement, performance features of various buses. The BIU implements all the bus operation for EU.

The queue size in BIU lets it maintain the EU provided with pre-fetched Instructions under most states without monopolizing the system bus. The 8086 BIU normally gets two bytes per fetching; in case a program 1 byte in the odd address and start again fetching two-byte words in the consequent even one.

Memory Segmentation in 8086 Microprocessor:

Microprocessor 8086 has 20 address pins, so maximum numbers of memory location, which can be connected with 8086 are 220 = 1MB location or 16 blocks of 64 K locations. The memory connected with 8086 divided into following four segments:

  1. Code Memory Segment:  It is used to store instructions code of a program.
  2. Data Memory Statement: It is used to store data bytes/words.
  3. Extra Memory Segment: It is an additional segment for storing data.
  4. Stack Memory Segment: It is used to store stack of data using PUSH/POP instruction.

Microprocessor 8085 vs Microprocessor 8086:

           Microprocessor 8085            Microprocessor 8086
It has 16 bit addressing busIt has 20 bits addressing bus
8085 does not support pipeliningIt supports pipelining
Instruction Queues are not supportedInstruction Queues are supported.

To know more about microprocessor click here

About Soumali Bhattacharya

I am currently invested in the field of Electronics and communication.
My articles are focused towards the major areas of core electronics in a very simple yet informative approach.
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