8085 Microprocessor: Interrupts,Functions & 7 Facts

Definition of Interrupt:

“Interrupt is the process of generating a momentary halt during program execution and permits peripheral devices to access the microprocessor”

8085 Architecture

Types of Interrupts:

Types of Interrupts according to delay:

• Maskable
• Non-maskable

Types of Interrupts according to grouping:

• Vector
• Non-vector

Types of Interrupts according to priority:

• TRAP
• RST 7.5
• RST 6.5
• RST 5.5

Block Diagram of 8085 Interrupts:

What is masking?

Masking can be implemented for the 4 hardware interrupts- RST 7.5, RST 6.5, RST 5.5 & INTR. In this figure, TRAP is NMI (Non Maskable Interrupt).

RST 7.5 alone has a F/F to recognise its edge transmission. The masking of interrupt can be done using SIM instruction. In additional a separate interrupt enables F/F is available to mask or allow the interrupts.

• The maskable interrupts are masked by default by means of the reset signal.
• The interrupt can be enabled by execution of EI instruction. So, to enable interrupts, after resulting the microprocessor the EI instruction must be used in 8085 microprocessor.
• The 3 RST interrupts could be masked by load up the suitable word variety in the accumulation and implementing SIM instruction. This is known as software-masking.
• All the maskable interrupts are disabled whenever an interrupt is recognized. So, it is essential to perform EI instruction every single time.
• Altogether, the maskable interrupts may be disabled by performing DI instructions. The instruction resets an interrupt enable F/F in the microprocessor. For the enabling purpose, instruction EI is utilized.

TRAP:

• It is non-maskable interrupt such that it need not to be enabled and cannot be enabled or disabled.
• It is accessible to user
• It is used for emergency situation such as power failure or energy shut off etc.
• It is edged as well as level triggered that is the i/p should goes high and stay in this condition to acknowledgement.
• TRAP has highest priority amongst all.

RST 7.5:

• Its priority is just after the TRAP.
• It is maskable such that both EI and DI operation can be possible.
• It is sued for the situation whose priority is just after emergency situation.
• It is positive edge triggered interrupt.
• It can be triggered with a very short duration pulse.

RST 6.5:

• Its priority is just after RST 7.5.
• Other specifications are as same as RST 7.5.

RST 5.5:

• Its priority is just after RST 6.5.
• Other specifications are as same as RST 7.5.

INTR:

• INTR is the lowest priority interrupt.
• This is edge as well as level triggered.
• Maskable and non-vectored type.
• Both EI and DI can be possible in this situation.

Operation of INTR:

The signal flow sequence is as follows to INTR goes high.

1. 8085 authorizations the status of the INTR, for carrying out an instruction.
2. If INTR signal is 1, then 8085 will complete its present instruction and an active-low interrupt will be acknowledged by an interrupt ACK.
3. Then the address of next instruction will be loaded in stack and will perform received instruction.

INTA:

• It is not the interrupt just used by the microprocessor sent the acknowledgement. The process should be enabled by instruction.
• During T₃ condition of the opcode fetch, 8085 checks repeatedly of every instruction. If interrupt finds the microprocessor will complete execution instruction and ready for the restart sequence.
• The restart sequence resets the interrupt F/F and active INTA upon receiving the signal.

Interrupt Call Locations:

The call locations for 8085 are

TRAP- 0024

RST 7.5- 003C

RST 6.5- 0034

RST 5.5- 002C

SIM Operation (Set Interrupt Mask):

SIM (Set Interrupt Mask) for 8085 is explained as follows

M 5.5 – it is basically set to 1 to reset 5.5 mask

M 6.5 – it is also set to 1 to reset 6.5 mask

M 7.5 – it is also set to 1 to reset 7.5 mask

MSE – to mask interrupt

R 7.5 – it is reset RST 7.5 F/F

SDE – serial data enable set to 1 for sending

SOD – serial output data to be sent

EXPLANATION:

• RST 7.5, 6.5 & 5.5 are maskable interrupts. The instruction EI and SIM utilized for enabling these.
• BIT 0 to 2 is either set or reset the mask for RST 6.5, 7.5 & 5.5.
• If a bit is set to 1, then the interrupt is masked off i.e., disable. If set as 0, the respective interrupt is enabled.
• If bit 3 is set to 1 to mask on bit 0 to 2.
• BIT 4 is additional control for RST 7.5. If it is set to 1 the RST 7.5 is reset.
• Bit 6 and 7 are serial output data where bit 6 is to enable SOD and bit 7 may be either high or low. The instruction DI disable all the interrupts.

PENDING REQUEST:

When 1 interrupt request is being served, other interrupts may occur resulting in pending request. When more than 1 interrupt occur simultaneously then interrupt having higher priority has served and interrupt having lower priority remain in the pending condition.

8085 microprocessor has an additional instruction called RIM (Read Interrupt Mask) to sense the pending interrupt.

RIM Operation (Reset Interrupt Mask):

RIM (Read Interrupt Mask) for 8085 is explained as follows

M 5.5:  This bit is set to 1 if RST 5.5 is masked. The bit 0 to 2 could be used for interrupt mask utilizing RIM instruction

M 6.5: This bit is set to 1 if RST 6.5 is masked.

M 7.5: This bit is set to 1 if RST 7.5 is masked.

IE:  It is set to 1 if all interrupts are enabled.

I 5.5: It is set to 1 when RST 5.5 is in pending condition.

I 6.5: It is set to 1 when RST 6.5 is in pending condition.

I 7.5:  It is set to 1 when RST 7.5 is in pending condition.

SID:  Serial Input Data; it will be either 1 or 0 for input purpose.

Vectored Interrupts:

TRAP, RST 7.5, RST 6.5, RST 5.5 (call location).

SOFTWARE INTERRUPTS VS HARDWARE INTERRUPT:

What is Stack?

Stack

A stack in 8085 microprocessor is a set of memory location in read-write memory specified by a programmer in a main program. These memory locations are utilized to store binary data momentarily during coding.

The initiation of the stack is defined in the program by executing the basic load instruction such as LXI SP. This generally load a sixteen bit memory address in the SP register.

Types of Stack:

1. PUSH
2. POP

PUSH – In the course of execution, PUSH is required to resolve the problem of certain register since the registers are prerequisite for some additional execution in consequent state. These contents move to certain memory location by a special function register is called PUSH.

Example-

                LXI SP, 2099 H

               LXI H, 42F2 H      

               PUSH H

1. Loads the contents of 2099H with SP register that is reserved in read-write memory as a state and the location begins from 2098H in moving upward for temporary storage.
2. LXI H, 42F2H describes the loading of H-L pair i.e., (42) is loaded in H and F2 is loaded in L.
3. PUSH H indicates that the content of H i.e., 42 stored in 2098H and the content of L i.e., F2 is stored in 2097 H.

POP – After completion of this operation this content which are saved in the temporary register are transferred back to the main memory by the operation of POP.

 Example –

                          LXI SP, 2099 H

                          LXI H, 42F2 H

                          PUSH H

                          DELAY COUNTER

                          POP H

The contents of register H-L pair are not destroyed. It is available of the delay counter in the content of the program counter. The content of the top stack location shown by SP appear into the register L and SP will increase 1.

The content of top of stack i.e., 2097 is shifted to 2098 and 2099 by 1 incarnated and from the temporary register the contents move to the main register.

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Soumali Bhattacharya

Hi, I am Soumali Bhattacharya. I have done Master’s in Electronics.
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