Engineering

Points of Discussions

• Introduction to AC Circuit
• Important terminologies related to AC Circuit
• Pure Resistive AC Circuit
  • Phasor Diagram of a purely resistive circuit
  • Power in a purely resistive circuit
• Pure Capacitive AC Circuit
  • Phasor Diagram of Pure capacitive circuit
  • Power in a purely capacitive circuit
• Pure Inductive AC Circuit
  • Phasor Diagram of Pure inductive circuit
  • Power in a purely inductive circuit

Introduction to AC Circuit

AC stands for alternating current. If the flow of charge from an energy source changes periodically, the circuit will be referred to as an AC circuit. The voltage and current (both magnitude and direction) of an AC circuit changes with time.

AC circuit comes up with additional resistance towards current flow as impedance and reactance are also present in AC circuits. In this article, we will discuss three elementary yet important and fundamental AC circuits. We will find out the voltage and current equations, phasor diagrams, power formats for them. More complicated yet basic circuits can be derived from these circuit, like – Series RC Circuits, Series LC circuits, Series RLC circuits, etc.

What is DC Circuit? Learn About KCL , KVL! Click Here!

Important terminologies related to AC Circuit

Analysing the AC circuit and studying them needs some basic knowledge of electrical engineering. Some of the frequently used terminologies are noted down below for references. Study them briefly before exploring the AC circuit family.

• Amplitude: Power flows in the AC circuit in the form of sinusoidal waves. Amplitude refers to the maximum magnitude of the wave that can be reached in both the positive and negative domains. The maximum magnitude is represented as Vm and Im (for voltage and current, respectively).
• Alternation: Sinusoidal signals have a period of 360^o. That means the wave repeats itself after a 360^o time span. Half of this cycle is referred to as alternation.
• Instantaneous value: Magnitude of voltage and current given at any instant of time is known as instantaneous value.
• Frequency: Frequency is given by the number of cycles created by a wave in once second time span. The unit of frequency is given by Hertz (Hz).
• Time period: Time period can be defined as the time span taken by a wave to complete one full cycle.
• Wave form: Wave form is the graphical representation of the propagation of waves.
• RMS values: RMS value means the ‘root mean square’ value. RMS value of any AC components represents the DC equivalent value of the quantity.

Pure Resistive AC Circuit

If an AC circuit only consists of a pure resistance, then that circuit will be called as Pure Resistive AC Circuit. There is no inductor or capacitor involved in this type of AC circuit. In this circuit, the power generated by the resistance and the energy components, voltage and currents, stay in an identical phase. That ensures the rise of voltage and current for the peak value or the maximum value occurs at the same time.

Let us assume the source voltage is V, the resistance value is R, the current flowing through the circuit is I. Resistance is connected in series. The below equation gives the voltage of the circuit.

V = V_m Sinωt

Now, from Ohm’s law, we know that V= IR, or I = V / R

So, the current I will be,

I = (V_m / R) Sinωt

Or, I = I_m Sinωt; I_m = V_m / R

The current and voltage will have the maximum value for ωt = 90^o.

Phasor Diagram of a purely resistive circuit

Observing the equations, we can conclude that there is no phase difference between the circuit’s current and voltage. That means the phase angle difference between the two energy components will be zero. So, there is no lag or lead in between voltage and current of the pure resistive AC circuit.

Power in a purely resistive circuit

As mentioned earlier, current and voltage remain in the same phase in the circuit. The power is given as a multiplication of voltage and current. Proposed for AC circuits, the instantaneous values of voltage and current is taken into considerations intended for the calculation of power.

So, power can be written as – P = V_m Sinωt * I_m Sinωt.

Or, P = (V_m * I_m /2) * 2 Sinω²t

Or, P = (V_m /√2) * (I_m/ √2) * (1 – Cos2ωt)

Or, P = (V_m /√2) * (I_m/ √2) – (V_m /√2) * (I_m/ √2) * Cos2ωt

Now for average power in ac circuit,

P = Average of [(V_m /√2) * (I_m/ √2)] – Average of [ (V_m /√2) * (I_m/ √2) * Cos2ωt]

Now, Cos2ωt comes as zero.

So, the power comes as – P = V_r.m.s *I_r.m.s.

Here, P stands for average power, V_r.m.s stands for root mean square voltage, and I_r.m.s stands for root mean square value of current.

Pure Capacitive AC Circuit

 If an AC circuit only consists of a pure capacitor, then that circuit will be called as pure capacitive AC circuit. There is not any resistor or inductor involved in this form of AC circuit. A typical capacitor is a passive electrical device that stores electrical energy in an electric field. It is a two-terminal device. Capacitance is known as the effect of the capacitor. Capacitance has a unit – Farad(F).

When voltage is applied across the capacitor, the capacitor gets charged, and after some time, it starts discharging when the voltage source is taken away.

Let us assume that the source voltage is V; the capacitor has a capacitance of C, the current flowing through the circuit is I.

The below equation gives the voltage of the circuit.

V = V_m Sinωt

The capacitor’s charge is given by Q =CV, and I = dQ / dt gives the current inside the circuit.

So, I = C dV/dt; as I = dQ/dt.

Or, I = C d (V_m Sinωt)/dt

Or, I = V_m C d (Sinωt) / dt

Or, I = ω V_m C Cosωt.

Or, I = [V_m /(1/ωC)] sin (ωt + π/2)

Or, I = (V_m / Xc) * sin (ωt + π/2)

Xc is known as the reactance of the AC circuit (specifically the capacitive reactance). The maximum current will be observed when (ωt + π/2) = 90^o.

So, the Im = Vm / Xc

Phasor Diagram of Pure capacitive circuit

Observing the equations, we can conclude that the circuit’s voltage leads over the current value by an angle of 90 degrees. The phasor diagram of the circuit is given below.

Power in a purely capacitive circuit

As mentioned earlier, the voltage phase has a lead over current by 90 degrees in the circuit. The power is given as a multiplication of voltage and current. For AC circuits calculations, the instantaneous values of voltage and current are taken into consideration intended for the calculation of power.

So, power for this circuit can be written as – P = V_m Sinωt * I_m Sin (ωt + π/2)

Or, P = (V_m * I_m * Sinωt * Cosωt)

Or, P = (V_m /√2) * (I_m/ √2) * Sin2ωt

Or, P = 0

So from the derivations, we can say that the average power of the capacitive circuit is zero.

Pure Inductive AC Circuit

 If an AC circuit only consists of a pure inductor, then that circuit will be called as pure inductive AC circuit. There is not at all resistors or capacitors are involved in this type of AC circuit. A typical inductor is a passive electrical device that stores electrical energy in the magnetic fields. It is a two-terminal device. Inductance is known as the effect of the inductor. Inductance has a unit – Henry(H). The stored energy might also be returned to the circuit as current.

Let us assume that the source voltage is V; the inductor has an inductance of L, the current flowing through the circuit is I.

The below equation gives the voltage of the circuit.

V = V_m Sinωt

The induced voltage is given by – E = – L dI/dt

So, V = – E

Or, V = – (- L dI/dt)

Or, V_m Sinωt = L dI/dt

Or, dI = (Vm/L) Sinωt dt

Now, applying integration on both sides, we can write.

Or, ∫ dI = ∫ (Vm/L) Sinωt dt

Or, I = (Vm/ ωL) * (- Cosωt)

Or, I = (Vm/ ωL) sin (ωt – π/2)

Or, I = (Vm/ XL) sin (ωt – π/2)

Here, X_L = ωL and is known as inductive reactance of the circuit.

The maximum current will be observed when (ωt – π/2) = 90^o.

So, the Im = Vm / X_L

Phasor Diagram of Pure inductive circuit

Observing the equations, we can conclude that the circuit current leads over the voltage value by an angle of 90 degrees. The phasor diagram of the circuit is given below.

Power in a purely inductive circuit

As mentioned earlier, a current phase has a lead over voltage by 90 degrees in the circuit. The power is given as a multiplication of voltage and current. For Ac circuits, the instantaneous values of voltage and current is taken into considerations utilized for the calculation of power.

So, power for this circuit can be written as – P = V_m Sinωt * I_m Sin (ωt – π/2)

Or, P = (V_m * I_m * Sinωt * Cosωt)

Or, P = (V_m /√2) * (I_m/ √2) * Sin2ωt

Or, P = 0

So, from the derivations, we can say that the inductive circuit’s average power is zero.

Topic of Discussion: MOS Capacitor

• Introduction of MOS Capacitor
• Interface charge of MOS Capacitor
• Working Principle in different states
• MOS capacitance
• MOS Threshold voltage

What is MOS Capacitor ?

To build a A MOS capacitor, the mostly needed and major thing is the gate-channel-substrate structure.

This particular type of capacitor has two-terminals which is mainly a semiconductor device; it is made of a metal contact & a dielectric insulator.

An extra ohmic contact is given at the semiconductor substrate.

MOS Structure

The MOS structure is mostly consisted of three things:

1. The doped silicon as the substrate
2. Oxide Layer
3. Insulator material: Silicon dioxide.

 Here, the insulating quality of the oxide which is uesd is quite good. The oxide-semiconductor’s density and width are very low at the particular channel accordingly.

 When a bias voltage is applied,  all the charges and interferences are prevented due to the infinite resistance of the respective insulator; hence in the metal some counter charges are produced in the same layer.

The counter charges and voltage which were produced previously are used in the capacitor to control the interface charge (majority carriers, minority carriers etc). However,  the ability of fabricating a conducting sheet of minority carrier at the boundary is essential for MOS design.

Interface Charge of a MOS capacitor:

This is typically associated to the shape of the electron energy band of the semiconductor adjoining the edge. At a very low voltage,the energy band is defined by means of different properties and constructions i.e., metalic and the semiconductors. In the equation below, all the changes happened due to applied bias and voltage i.e., it becomes flat band is shown as

Where,

Ø_m and Ø_s  = work functions of the metal and the semiconductor,

rX_s = semiconductor’s electron affinity,

E_c =  the energy of the conduction band edge, and

E_F = Fermi level at zero voltage.

MOS Capacitor at Zero Bias and Applied Voltage:

In this stable state, no current flow is observed in the perpendicular direction towards the high resistance of the insulator layers.

 Hence, we consider the Fermi level as constant inside the semiconductor, No other biasing will change its value.

The shifted or constant Fermi Level is shown by,

E_Fm – E_Fs = qV.

This is called quasi-equilibrium situation where the semiconductor can be used as thermal equilibrium.

When a voltage is applied in a MOS structure with a p-type semiconductor, it seems to grow upward and makes the flat band voltage negative.

In depletion mode or region, it becomes V >V_FB                                               

With the increasing applied voltage and a bigger and greater energy band the difference in between the Fermi level and at the end of the conduction band at the semiconductor interface starts decreasing as well with respect to the Fermi level. Hence it becomes V = 0 V.

In higher applied voltage, the  electron concentration volume at the interface will cross the doping density of material.

ψ denotes potential differences of the semiconductors, when a place X is chosen in the semicon.

By taking consideration of electron equilibrium information, the intrinsic Fermi level Ei contracts to an different energy level qϕb from the actual Fermi level E_F of selected doped semiconductor material,

 Φ = V_th ln (N_a/n_i)

MOS Capacitance:

A MOS capacitor is designed with the metallic contacts with the neutralised sections inside a doped semiconductor material. The semiconductors is also allied in series with an insulator usually prepared by silicon oxide.

The series connection between these two is presented by ,

 C_i = Sε_i/d_i,

Wherever,

• S = Area of MOS capacitor,
• C_s  = capacitance of the active semiconductor,

• CMOS = The semiconductor capacitance can be calculated as,

Wherever,       

• Q_s =  total charge density / area
• ψ_s is the surface potential.

Threshold Voltage of MOS Capacitor:

The threshold voltage is measured as V = V_T . This thereshold voltage is one of the significant parameters which denotes in metal insulator semiconductor devices. The prevailing inversion may takes place if the surface potential ψs turn out to be equivalent by term 2ϕb.

The charge at the insulator-semiconductor interface of depletion layer is expressed as,

The threshold voltage applied to the ground potential is shifted by VB. A change in a MOSFET occurs when the conduction layer of moveable electron is kept at approximately fixed potentials. By taking into consideration that the inversion layer is at ground, The voltage V_B is biasing the active junction amongst the inversion layer and speified substrate, and capacity of charge changeablity at depletion layer. In this case, the threshold voltage turn out to be,

The threshold voltage is changed if the surface conditions at the semiconductor oxide interface and differs within the insulated layer. The sub-threshold is hereby overlapped with the threshold voltage and the moveable carriers is increasing exponentially with the increment in applied voltage.

For more about MOSFET basics and others electronics related article  click here

Points of Discussion : DC Circuits

1. Introduction to DC Circuits
2. Kirchhoff’s Laws
3. Kirchhoff’s Current Law (KCL)
4. Kirchhoff’s Voltage Law (KVL)
5. Node Voltage Method
6. Mesh Current Method
7. Loop Current Method
8. Some Important Questions related to DC Circuits

Introduction to DC Circuits

DC stands for Direct Current. If the energy source phase doesn’t change with time, then the circuit will be referred to as DC Circuits. Primary energy sources for DC Circuits are batteries or similar steady power suppliers. They have a range from 5 Volts to 24 Volts. Seeing the energy symbol of a circuit, one can understand whether it is AC Circuit or DC Circuits. The symbols are given below.

Kirchhoff’s Laws

Gustav Robert Kirchhoff was an eminent physicist of German origin. His research related to electrical circuits gave us two primaries yet the most critical laws for circuit analysis. These laws are typically known as Kirchhoff’s laws. He had come up with laws for both current and voltage. They are popularly known as – Kirchhoff’s Current law and Kirchhoff’s Voltage Law. These laws are fundamental rules for DC circuits analysis.

Before studying Kirchhoff’s laws, one should have basic circuit properties of nodes, junctions, loops, mesh, branches, etc. Some definitions are given below; please check the circuit analysis article for more such primary terminologies.

• Node / Junctions: Node or junction in a circuit is known as the connecting point of two or more numbers of components.
• Loop: A loop in a circuit is defined as a closed path starting from a specific node, traveling through any part of the circuit, and ends at that specific point. There is a point to be remembered that the path can travel any circuit part only for once.  A loop can include or overlap with any other loop of the circuit.
• Mesh: Mesh can be said as the smallest loop possible in a circuit that has no overlap and doesn’t include any other loop within it.
• Kirchhoff’s Current Law is often interpreted as the First Law of Kirchhoff’s or Kirchhoff’s Junction law. It deals with the current equations of a node or junction.
• Kirchhoff’s Voltage law is often interpreted as the Second Law of Kirchhoff’s or Kirchhoff’s loop law. It deals with the voltage equations of a loop.

Kirchhoff’s Current Law (KCL)

“Kirchhoff’s current law states that the summation of the incoming current to a node is equal to the summation of the outgoing current from the node.”

Mathematically it can be stated as the following equation.

∑I_in = ∑ I_out

From the above image, we can observe that the currents I₁ and I₄ are incoming to the node while I₂ and I₃ are outgoing currents. So, we can write according to Kirchhoff’s Current Law that –

I₁ + I₄ = I₂ + I₃

Or, I₁ + I₄ – I₂ – I₃ = 0

Concept Check: What will be the current value for the branch I₅? Provided that I₁= 2 mA, I₂= 1 mA, I₃= 4 mA, I₄= 1 mA and I₆= 2 mA.

Solution: To solve this type of problem of DC Circuits, first find out the desired node. Then separate the incoming and outgoing current components. Then apply Kirchhoff’s current law and find out the solution.

The incoming currents are I₁, I₃, I₄.

The outgoing currents are I₂, I₅, I₆.

The missing component is I₅, which is outgoing.

Now, from KCL, we know that –∑I_in = ∑ I_out

So, we can write –

I₁ + I₃ + I₄ = I₂ + I₅ + I₆

Or, I₅ = I₁ + I₃ + I₄ – I₂ – I₆

Or, I₅ = 2 mA + 4 mA + 1 mA – 1 mA – 2 mA

Or, I₅ = 4 mA

Kirchhoff’s Voltage law (KVL)

Kirchhoff’s Voltage Law states that the voltage around a loop of the circuit equals zero, and the algebraic sum of voltage drop at each branch in that loop is equal zero also.

Mathematically it can be stated as the following equation.

∑ V_n = 0

V_n represents the voltage around n elements or branch of the loop.

From the above image, we can write that,

V_AB + V_BC + V_CD + V_DA = 0

Kirchhoff’s voltage law has few characteristics. Some of them are –

• While analyzing a circuit, if you start your path with a node, do not include any other loop in your path, and end your path in the same node, then the sum of voltage through that path will be zero.
• The path can be in any direction; the Clockwise or anti-clockwise path does not affect Kirchhoff’s voltage law.
• A typical complex circuit may have many loops. KVL is valid for each and every possible loop of the circuit.

Node Voltage method

The node voltage method is another useful method for the analysis of the DC circuit. It is derived from Kirchhoff’s current law. SPICE – a simulator software contains this method. Actually, this method is more comfortable to implement and analyze the whole circuit. Using the method helps us to get rid out of Kirchhoff’s voltage law if we want to.

• Node Voltage: Node voltage is a concept needed for the Node Voltage Method. This can be defined as the potential difference between two nodes.

Steps to follow: The node Voltage method can be applied to the DC circuits by following the below-mentioned steps.

• Select a reference node. In most cases, the ground node is elected.
• Name all the other nodes of the circuit.
• Start with the nodes, which seems to be easy. The energy source (preferably voltage source) node connected with the reference node would be more comfortable.
• Now apply Kirchhoff’s current law for every node. Also, do the calculations of hm’s law.
• Find out the solutions for all of the node voltages.
• Find out any current of the circuit with the help of Ohm’s law.

Mesh Current Method

The mesh current method is another efficient method for DC circuit analysis. It is derived from Kirchhoff’s Voltage Law, and a new method named “Loop current method” is derived from this method. It has an added advantage over other circuit analysis methods as it does not require to solve a 2E number of circuit equations (E stands for the number of elements of the circuit). Studying this method needs an adequate level of understandings of the concept of loops and meshes.

• Loop current: Loop current is a concept needed for this method. It is defined as the current through any loop or mesh of the circuit.
• Superposition principle: Superposition stands for general addition. Here superposition principle states that loop currents can be added together to get the actual current element.
• Linearity: Linearity characteristics help to use the principle of superposition. Linearity is multiplying voltage with a constant and getting the current as constant the multiplied product.

Steps to follow: Mesh current method can be applied by following the below-mentioned steps.

• Mark the meshes (known as open windows of the circuit).
• Choose a specific constant current direction (either clockwise or anti-clockwise), which all be applied for every mesh. Also, give current variables to each mesh.
• Apply Kirchhoff’s Voltage law for each mesh and write down the equations.
• Calculate the resulting system for all the mesh equations.
• Using Ohm’s law, find out the desired current and voltage components.

Loop current Method

We can say that the Loop current method is an updated version of the Mesh Current method. This method is popular and helpful for non-planar circuits.

Steps to follow: loop current method can be used to analyse DC circuits using the below-mentioned steps.

• Mark the meshes (known as an open window of the circuit). Also, identify the loops.
• Choose a specific constant current direction (either clockwise or anti-clockwise), which all be applied for every mesh. Also, give current variables to each mesh or the loops.
• Calculate the resulting system for all the mesh and loop current equations.
• Using Ohm’s law, find out the desired voltage and current component.  

Some important questions related to DC Circuits

1. What is the main idea behind Kirchhoff’s current law?

Answer: The main idea behind Kirchhoff’s current law is the theory that charges cannot be accumulated at one point.

2. Write some limitations of Kirchhoff’s laws.

Answer: Kirchhoff’s both laws have some limitations. They are listed below.

• Kirchhoff’s current law comes with the assumption that conductors and wires are the only media for the flow of current. In reality, in high-frequency circuits, we can observe the flow of current in open circuits as standard conductors work as transmission lines.

• Kirchhoff’s Voltage law comes up with the assumption that every closed loop of the circuit will be free from the effect of the magnetic field, more specifically, the fluctuating magnetic field. But, in the high-frequency circuits, this condition doesn’t get satisfied.

3. Nodal analysis is based on the law of energy conservation—state whether the given sentence is true or false.

Answer: False. Nodal analysis is based on Kirchhoff’s current law, and also Kirchhoff’s first law supports the conservation of charges, not energy.

4. What is the effect on the circuit’s current if the energy sources are connected in parallel?

Answer: The current of the whole circuit gets increased.

Topic of Discussion: MOS Transistor

• What is MOS Transistor ?
• Working principle of MOS Transistor
• V-I Characteristics
• Utilization

What is MOS Transistor?

A Metal-Oxide-Semiconductor or ‘MOS’ transistor is recognized for its operation as an ideal switch operation.  A MOS transistor chip performs as a reliable current and capacitor of the transistors and its wires.

In the figure below, we can see some regular schematics of MOS transistors that are used commonly

We typically use the different terminal symbols i.e., figure when the body along with the substrate or the well-connection needs to be shown.

Working Principle of MOS Transistor:

For being a majority carrier device, a MOS transistor carries the current between its source and drain. This transistor gets regulated with a regular voltage applied to the gate of the respective MOS. In an n-MOS transistor, the electrons act as a the majority carrier while in a p-MOS type, Holes is acts as majority carriers. A MOS transistor is examined with an isolated MOS structure with a gate and body included to know about its properties or behavior’s figure below gives a simple structure of MOS. The top most layer of the MOS structure is made of a conductor.

This is very good for carrying currents for any charge; which is acknowledged as the gate. The transistors which were made at the very beginning, used metal gates; with the up growing time period, the transistor gates were changed and polysilicon is being used. The intermediate mid-layer of a MOS is made of a thin insulating film of silicon oxide which is usually identified as the gate oxide. The layer at the lower level is doped with silicone.

If we apply a negative voltage in the gate, a negative charge on the gate is produced. Beyond the gate, the holes are attracted toward the region as the mobility carriers are charged with positive energy. This is called the accumulation mode.

In figure (b), a A very minimal amount of voltage is supplied to the gate, which we get from a positive charge on the gate. To form a depletion region, the holes of the body which are generated from repulsion, get accumulated under the gate.

In figure (c), Threshold Voltage Vt is supplied and few electrons gets attached to that area.

Inversion Layer:

The conductive layer of the electrons in the p-type body is considered as an the ‘inversion layer’.

Here, the threshold voltage depends on two parameters, they are –  1. MOS’s dopants 2. Oxide layer’s thickness. It is regularly positive but they also can be made into negative ones. The nMOS transistor has piles of MOS between both the n-type regions called the source and the drain.

At this point, the gate-to-source voltage V_gs < the threshold voltage (V_t). The source and drain are having no of free electron in both sides. When the source is not working i.e., in ground state, the junctions are said to be reverse-biased, so no current flows. When the transistor is said to be OFF, this mode of operation is called cut-off.

the current is 0 if we compare it with an ON-transistor. The gate voltage is higher than the threshold voltage. Now if an inversion region of electrons which are the channel, makes a bridge between the source and drain and create a conductive path and turns the transistor ON. The increase in the number of total carriers and the conductivity increases are proportionate to each other with respect to the applied gate voltage.

The drain voltage – Source voltage is given as:

 V_DS = V_gs – V_gd . When, V_DS = 0 (i.e., V_gs = V_gd),

there is no such electric field exists to produce current from drain to source.

When, The voltage (V_ds ) is applied to the drain, and the current I_ds carries through the channel of drain to the source. If V_ds becomes larger than that V_gd < Vt, the channel doesn’t seem to have any change near the drain and hence it is in off state. Even after this, the conduction is being continued with the help of the drifted electron which is generated by the +ve voltage.

 When the electrons reached to the termination of the channel, the depletion region adjoining the drain gets accelerated in the direction of it. The injected electrons accelerate this process.

Saturation Mode:

In this mode, the current Ids is controlled by the gate voltage and gets terminated by the drain only when it reaches beyond the drain voltage.

V-I Characteristics of MOS Transistor

The V-I characteristics of MOS transistor has three regions of operation:

• The Cut-off or sub-threshold region.
• The Linear region.
• The Saturation region.

The length of channel in an n-MOS transistor is lengthier and the electric field amongst the source to drain is comparatively low. The channel is generally identified as the ‘long-channel’, ideal, 1^st order, or Shockley model while characterized as a figure.

The long-channel model represents a current that carries through an OFF transistor. It is very low or 0.  The gate attracts carriers to build a channel in its OFF state (V_gs> V_t). At the source to drain region, the electrons keep flowing at a uniform speed.

Charge of the capacitor plate is given by – Q = CV.

Thus, the charge in the channel Q_channel is

                                    Q_channel = C_g(V_gc – V_t)

The above graph shows the I-V characteristics for the transistor.

 In the particular graph, the current which flows is ‘0’ for gate voltages underneath V_t. The current has increasing when the gate voltage increases accordingly linearly with V­_ds for small V_ds. As V_ds approaches the saturation point V_dsat = V_GT, current declines and eventually turn out to be independent.

 The pMOS transistors behave in a reverse way than the n-MOS transistor  so all voltages and currents are negative here.Here the current flows from source to drain and the fluidity of holes in a silicon is usually lower than that of the electrons.

 So, a p-MOS transistor produces less current than n-MOS transistor of same size and features. Here µ_n and µ_p = mobility of electrons and of holes in n-MOS and p-MOS transistors, respectively. The mobility ratio µ_n /µ_p lies between 2–3. The p-MOS transistors have the identical geometry like a nMOS.

For more about MOSFET and others electronics related article  click here

Topic of Discussion: CMOS Amplifier

• What is CMOS ?
• What is CMOS Amplifier ?
• Input Offset voltage
• Different parameters in CMOS amplifier
• Applications of  CMOS  Amplifier

What is CMOS ?

CMOS:

CMOS is acronym of Complementary Metal Oxide Semiconductors. It is one of the types of Metal oxide Field Effect Transistor and it is a unipolar device unlike BJTs.

What is a CMOS Amplifier ?

CMOS Amplifier:

CMOS amplifiers (complementary metal–oxide–semiconductor amplifiers) are universal analog circuits utilized in personal computer, laptops, audiovisual device, mobilephones, cameras, communication systems, different biomedical applications, to many more other applications. In high performing CMOS amplifier circuitry, transistors are generaly used. Transistor not only utilzed to amplify the signals but those are also utilized as active load to attain high gain and output swing in comparison to resistive loading blocks.

The above figure shows a two stage CMOS Amplifier.

Some of the critical parameters which represents the amplifiers are – 1. Range of the supplied voltage, 2. Response to frequencies, 3. Response to the Noises, etc.

Input Voltage Range:

The range designates a “permissible” I/P voltage that will generate a linear, non-distorted O/P signal.

                                          V_DS>V_GS – V_T

V_G is the input voltage, V_D is V_DD -V_SAT for PMOS.

From the above explanation, the input voltage is able to swipe to some degree above the voltage V_DD. The M₁₅ and M₁₆ are constructed to oppose to that current direction of M₁₄. Nonetheless, V_DM12 is not equal to V_DM14.

Signal Path of CMOS Amplifier:

Signal-path represents the path through which the signal reaches to the output from the input. The signal path employed to investigate the freq-response, stability, and many more factors.

As the standard CS amplifier has high gain, the Miller effect will increase the total input capacitance. Any capacitance between output and input can be seen as capacitance at the input to the ground with the multiplication of (1 + Gain).

Load in CMOS Amplifier:

We can observe two varieties of active load in CMOS Amplifier: The diode connected MOS or current source MOS.

1. It represents the output associated with a source of current. The current source acts as ‘Load’ for the output.
2. By reason of V_gs of the active load is constant. Resistance value is r₀ = 1/λI_d, where I_d is drain current. The low frequency or direct current (DC) gain,

                        A_v = g_mn (r_oM16 // r_0casp) g_M17 (r_0M18 // r_0M17)

Typical load problem:

• Buffer configuration is a severe test for instability. It is found that a need of having a greater compensation capacitor for this purpose.

• It cannot drive a small load resistor.

CMOS Amplifier Parameters:

Input Offset:

The offset voltage is V_ref – V_I

The offset voltage of the amplifier has presented in above figure. This is measured from the disparities by taking considerations of paramter such as threshold voltage, load resistance, etc.

Common Mode Rejection Ratio (CMRR):

“CMRR is given by the ratio of the gain of the amplifier in differential mode to the gain of the amplifier in common mode.”

Power Supply Rejection Ratio(PSRR):

Power Supply Rejection Ratio or PSRR is given by the ratio of Output voltage to the input voltage. PSRR describe the noise rejection of CMOS amplifier.  Typical method to improves the power supply rejection ratio is generally by by means of a cascode current source or sink (this is because of high output resistance value).

Slew Rate and Settling Rate:

• High slew rate
• Small compensation capacitorIncrease the operating current

Settling time is equivalent to T_settling parameter and

Slew Rate = V_idmax

Noise:

For 1 μA, 7.8 × 10¹² electrons passing every second will generate a noise of 7800 Giga Hertz.

1. The higher input transistor is required to reduce the noise level.

2. Increase in operating current is also required.

3. White and short noise  is mostly constant during the total operation

4. Flicker noise

Compensation in Amplifier:

Compensation is required to ensure stability in opamp. A CMOS Amplifier, loop-gain and phase are the prameter generally specify the Amplifier’s stability. The Op-Amp is generally constructed in a closed-looped for gain and phase analysis puropse. Suitable capacitance, resistance and biasing is also required for the compensation of amplifier.

Uses of CMOS Amplifier:

• This complementary metal–oxide–semiconductor amplifiers are utilized in personal different electronics consumer products such as computer, laptops, audiovisual device, mobile phones, cameras etc.
• These are one of the important component of telecom appliance
• Different biomedical applications utilized these type of amplifier nowadays. There are many more other applications of CMOS amplifier and list is increasing.

For more about MOSFET basics and others electronics related article  click here

Read more about Log & Antilog Amplifier.

Bildnachweis – “Freundschaft an Bord”(CC DURCH-NC-ND 2.0) durch Elf-8

Diskussionspunkte

• Einführung in die Parabolreflektorantenne
• Übersicht der Parabolreflektorantenne
• Anwendungen der Parabolreflektorantenne
• Eigenschaften
• Geometrieanalyse
• Richtwirkung der Parabolreflektorantenne
• Apertureffizienz der Parabolreflektorantenne
• Mathematische Probleme

Einführung in die Parabolreflektorantenne

Antenne oder Strahler ist ein Mittel zum Strahlen und Empfangen elektromagnetischer Informationen. Parabolreflektorantenne ist eine der weit verbreiteten Antennen. Es ist ein besonderer Typ von Reflektorantennen. Der Einsatz von Reflektorantennen begann mit dem Beginn des Zweiten Weltkriegs mit der Weiterentwicklung der Kommunikationstechnologien.

The most straight-forward reflector and more comfortable to implement the reflector antenna is ‘Plane Reflector’ antenna. There are some other types of reflectors also, like – corner reflector, parabolic reflector, Cassegrain reflectors, spherical reflectors. Parabolic reflectors have another type known as ‘Front fed parabolic reflector antenna’.

Was ist eine Hornantenne? Erkunden hier!

Übersicht der Parabolreflektorantenne

Die Strahlungsparameter einer Reflektorantenne können durch Verbesserung des Strukturmusters des Bodens verbessert werden. Auf diesem Gebiet kommt für diesen Parabolreflektor die optische Wissenschaft ins Spiel. Die optische Mathematik beweist, dass einfallende parallele Strahlen durch Reflexion an einer parabelförmigen Struktur zu einem bestimmten Punkt (bekannt als Brennpunkt) konvergiert werden können.

Die reflektierten Wellenformen treten als paralleler Strahl aus. Dies ist ein mathematisches Phänomen, das als “Reziprozitätsregel” bekannt ist. Der proportionierte Punkt wird als Scheitelpunkt bezeichnet. Die ausgehenden, reflektierten Strahlen werden als kollimiert bezeichnet (da sie parallel sind). Obwohl die praktischen Beobachtungen gezeigt haben, dass die austretenden Strahlen nicht als paralleler Strahl bezeichnet werden können, unterscheiden sie sich geringfügig von der richtigen Form.

Der Sender dieser Antenne befindet sich im Allgemeinen an den Brennpunkten der Schale oder des Reflektors. Diese Art der Einrichtung wird als “Front-Feed” bezeichnet. Wir werden im nächsten Teil dieses Artikels eine Analyse dieser Art von Parabolreflektoren diskutieren.

Was macht eine Übertragungsleitung? Erforschen!

Anwendungen der Parabolreflektorantenne

Parabolreflektoren sind eine der weit verbreiteten, hocheffizienten Antennen, deren Nachfrage von Tag zu Tag steigt. Vom Empfang des Signals für unser Fernsehgerät bis zur Übertragung des Signals für die Raumstationen findet dieser Antennentyp Anwendungen in nahezu allen Bereichen der Kommunikationstechnologie. Einige der bemerkenswerten sind – auf Flughäfen, in Satelliten, in Raumstationen, in Teleskopen usw.

Eigenschaften

Einige signifikante Eigenschaften des Parabolreflektors sind unten angegeben. Die Eigenschaften betreffen Aperturamplitude, Polarisationseigenschaften, Phasenwinkel usw.

• Der Magnitudenanteil hängt vom Abstand der Einspeisung zur Reflektoroberfläche ab. Die Proportionalität variiert von Struktur zu Struktur. Wie bei einer parabelförmigen Form ist sie umgekehrt proportional zum Quadrat des Radius der Parabel, und bei einer zylindrischen Struktur ist die Beziehung umgekehrt proportional zu ρ.
• Der Brennpunkt des Reflektors wirkt für verschiedene Arten von geometrischen Konfigurationen unterschiedlich. Die zylindrische Struktur hat eine Linienquelle und parabolische Strukturen haben eine Punktquelle.
• Wenn der Vorschub lineare Polarisationen parallel zur Zylinderachse aufweist, besteht keine Möglichkeit von Kreuzpolarisationen. Parabolische Strukturen haben nicht die gleiche Eigenschaft.

Überprüfen Sie das Strahlungsmuster von Yagi Uda Antenne!

Geometrische Analyse

     Wenn eine geometrisch perfekte Parabel um ihre Achse gedreht wird, entsteht eine andere Struktur. Diese Struktur ist als Parabolreflektor bekannt. So entsteht ein parabolisch geformter Reflektor. Es gibt einen bestimmten Grund für die Form dieses Reflektors. Die parabolische Form hilft, aus den austretenden Strahlen eine einfache und ebene Wellenform zu erzeugen.

     Aus dem Bild können wir ersehen, dass die geometrische Länge OP + PQ einen konstanten Wert für das Entwerfen ergibt.

Wir können schreiben, OP + PQ = 2f; 2f ist der konstante Term.

Nehmen wir das an OP = r und so kommt PQ als PQ = r * cosϴ.

Nun ist der Wert von OP + PQ nach dem Ersetzen der Werte,

OP + PQ = r + r * cosϴ = 2f

Oder r (1 + cosϴ) = 2f

Oder r = 2f / (1 + cosϴ) = f * sec²(ϴ / 2)

In der Antennentheorie müssen wir nun die Grundlagen des Koordinatensystems in Form von Sachleistungen halten. Die obige Gleichung kann in rechteckigen Koordinatensystemen unter Verwendung von x`, y`, z` geschrieben werden. Das ergibt die folgende Form.

r + r * cosϴ = √ [(x`) 2 + (y`) 2 + (z`) 2] + z` = 2f

Lassen Sie uns den Einheitsvektor herausfinden, der senkrecht zur Tangente des Reflexionspunktes ist.

f – r * cos²(ϴ / 2) = 0 = S.

Durch einige Rechenoperationen finden wir den Einheitsvektor. Es wird unten beschrieben.

n = N / | N | = – (a) `<sub>r</sub> cos (ϴ / 2) + – (a) `_ϴ Sünde (ϴ / 2)

Mithilfe der geometrischen Analyse können wir nun einen Ausdruck für den Neigungswinkel finden. Es wird unten beschrieben.

tan (ϴ₀) = (d / 2) Z.₀

Das Z₀ ist die Messung der Entfernung von der Achse zum Brennpunkt. Mathematische Ausdrücke können es auch darstellen.

Z₀ = f – [(x₀² + y₀²) / 4f]

Oder Z.₀ = f – [(d / 2)²/ 4f]

Oder Z.₀= f – d² / 16f

Überprüfen wir den Wert von tan (ϴ₀) nach dem Ersetzen des Wertes von Z0.

tan (ϴ₀) = [(f / 2d) / {(f / d)² – (1/16)}]

Entdecken Sie die Anwendungen der Helixantenne! Klick hier!

Richtwirkung der Parabolreflektorantenne

Bevor wir uns mit der Richtwirkung einer Parabolantenne befassen, informieren Sie uns über die Richtwirkung einer Antenne.

Die Richtwirkung einer Antenne ist definiert als das Verhältnis der Strahlungsintensität einer Antenne in einer bestimmten Richtung zur gemittelten Strahlungsintensität über alle Richtungen.

Die Richtwirkung wird als Parameter zur Berechnung der Gütezahl der Antenne betrachtet. Der folgende mathematische Ausdruck beschreibt die Richtwirkung.

D = U / U.₀ = 4πU / P._rad

Wenn die Richtung nicht angegeben ist, ist die Standardrichtung die Richtung der maximalen Strahlungsintensität.

D_max = D₀ = U._max / U.₀ = 4πU_max / P_rad

Hier ist ‘D’ die Richtwirkung und hat keine Richtung, da es sich um ein Verhältnis handelt. U ist die Strahlungsintensität. U._max ist die maximale Strahlungsintensität. U.₀ ist die Strahlungsintensität der isotropen Quelle. P._rad ist die gesamte abgestrahlte Leistung. Seine Einheit ist Watt (W).

U = ½ r² * | E (r, ϴ = π) |² * √ (ε / μ)

Für U (ϴ = π) und Ersetzen des Energiewerts E wird aus dem vorherigen Wert –

U (ϴ = π) = [16 π² f² * Pt * | ∫.₀ ^ϴ tan (ϴ / 2) * √ (G._f (ϴ)) dϴ |²] / 4πλ²

Die Direktivität kommt als – D = U / U.₀ = 4πU / P._rad

Oder D = [16 π² f² * | ∫.₀ ^ϴ tan (ϴ / 2) * √ (G._f (ϴ)) dϴ |²] /²

Apertureffizienz der Parabolreflektorantenne

          Der mathematische Ausdruck für die Parabolreflektorantenne ist unten angegeben.

          ε_ap =_s * ε_t * ε_p * ε_x * ε_b * ε_r

Hier

ε_ap repräsentiert die Apertureffizienz.

ε_s ist Spillover-Effizienz. Es kann als der Teil der Leistung definiert werden, der von der Einspeisung übertragen und von der Oberfläche der Reflexion parallel geschaltet wird.

ε_t repräsentiert die Effizienz der Verjüngung. Es kann als die Singularität der Streuung der Größe für das Feed-Design über die Oberfläche des Reflektors beschrieben werden.

ε_p gibt uns die Effizienz der Phase. Es kann als die Gleichmäßigkeit der praktischen Feldphase über die Ebene der Apertur beschrieben werden.

ε_x repräsentiert die Effizienz der Polarisation.

ε_b ist die Effizienz des Rückstands.

Und ε_r stellt die Fehlereffizienz dar, berechnet über die gesamte Reflektorfläche.

Mathematisches Problem

1. Eine Parabolreflektorantenne hat einen Durchmesser von 10 Metern. Das f / d-Verhältnis wird mit 0.5 angegeben. Die Betriebsfrequenz ist auf 3 GHz eingestellt. Die Antenne, die mit dem Reflektor gespeist wird, ist symmetrisch aufgebaut. Es ist auch gegeben, dass –

G_f (ϴ) = 6 cos²ϴ; wo ϴ^o ≤ ϴ ≤ 90^o und null an jedem anderen Punkt.

Berechnen Sie nun i) die Apertureffizienz (ε_ap). ii) Richtwirkung der Antenne. iii) Verjüngungseffizienz und Effizienz des Überlaufens. iv) Ermitteln Sie die Richtwirkung der Antenne, wenn die Aperturphasenabweichung auf π / 4 Radian eingestellt ist.

Lösung:

          Wir wissen, dass der Neigungswinkel durch den folgenden Ausdruck gegeben ist.

tan (ϴ₀) = [(f / 2d) / {(f / d)² – (1/16)}]

Oder tan (ϴ₀) = [(0.5 · 0.5) / {(0.5 · 0.5) – (1/16)}]

Oder tan (ϴ₀) = 0.25 / 0.0625

Oder ϴ₀ = 53.13^o

Die Apertureffizienz ist gegeben als –

ε_ap = 24 [(Sünde² (26.57^o) + ln {cos (26.57^o)}]² * Kinderbett²(26.57^o)

oder ε_ap = 0.75

Der Öffnungswirkungsgrad beträgt also 75%.

Lassen Sie uns nun die Richtwirkung der Antenne herausfinden.

Es kann wie folgt berechnet werden.

D = 0.75 * [π * (100)]²

Oder D = 74022.03

Oder D = 48.69 dB.

Die Überlauffrequenz beträgt ε_s.

ε_s = 2 cos³ |₀ ^53.13 / 2 cos³ |₀ ⁹⁰ 

oder ε_s = 0.784

Die Spillover-Effizienz der Antenne beträgt also 78.4%.

Jetzt Zeit für die Berechnung der Effizienz des Gewindeschneiders. Die Tapper-Effizienz wird als & epsi; dargestellt_t.

ε_t = (2 · 0.75) / 1.568

oder ε_t = 0.9566

Der Tapper-Wirkungsgrad für die Parabolreflektorantenne beträgt also 95.66%.

Jetzt wird die Aperturphasenabweichung auf π / 4 Radian eingestellt.

Das heißt m = π / 4 = 0.7854

Wir wissen, dass D / D.₀ ≥ [1 – m²/ 2]²

Oder D / D.₀ ≥ [1 – (0.7854 * 0.7854) / 2]²

Oder D / D.₀ ≥ 0.4782737

Oder D ≥ 0.4782737 * D._0.

Oder D = 0.4782737 * 74022.03

Oder D = 35402.8

Oder D = 45.5 dB.

Die Richtwirkung unter den gegebenen Bedingungen beträgt 45.5 dB.

Cover Image Credit – Service Depicted: Air Force
Camera Operator: SSGT LOUIS COMEGER, Hammer Ace SATCOM Antenna, marked as public domain, more details on Wikimedia Commons

Points of Discussions

• Introduction
• Geometrical Analysis and Configurations
• Operational Modes
• Normal Mode
• Axial Mode
• Helical antenna design
• Helical antenna applications

Introduction to Helical Antenna

            To define a helical antenna, we must know the correct definition of the antenna previously. As per to IEEE standard definitions of antennas or radiators,

“An antenna is a medium for transmitting and receiving radio waves”.

There are several adaptations of antennas. Some of them are – dipole antennas, horn antennas, log-periodic antennas, patch antennas, broadband antennas etc.

          The helical antennas or helix antennas are one of the categories of broadband antennas. It is one of the most straightforward, primary and realistic antennas with a helical structure, made up of conducting wire-wound.

What is a horn antenna? Explore here!

Geometrical analysis and configuration

          Helical antennas or helix antennas generally come with a ground plane which has the ability to accept distinct forms. To establish a typical helix connection with the ground plane, the ground plane’s diameter should be minimum of 3*λ/4. Although, the plane may be transfused into a cylindrical shaped crater. At the feed point, the transmission lines meet with the antenna.

          The geometrical description of a helix antenna typically consists of N number of turns, the diameter D and the distance between two helical loop S.

The whole length is given by –> L = N S.

The conductive wire’s whole length is given by –> L_n = N L₀ (It carries the current primarily obviously!)

 Or, L_n = N √ (C² + S²); L₀ = √ (C² + S²)

L₀ represents the dimension of the wire between two helical loops. It actually gives the length.

C represents the whole circumference of a spiral loop, and it is given by -> π D.

There is another spiral or helix antenna’s parameter, which is also very important. It is represented by the Greek alphabet alpha(α) and termed as ‘pitch angle’. This angle is generally the measurement of the line’s angle – normal to the helix wire and a steep ground to the helix axis. The mathematical expression is given below.

α = tan^-1 (S/C)

or, α = tan^-1 (S/ π D)

By carefully observing the equation, it can be concluded that when the angle tends to 0 degrees, the winding gets trampled; as a result, the helix antenna gets reduced and becomes similar to a simple loop antenna. Again, when the angle becomes 90 degrees, the antenna becomes a linear wire. When the angle is less than 90 degrees and greater than 0 degrees, then a practical helix has a finite value of circumference.

The architectural parameters can change the radiation properties of the helix antennas. Controlling the geometrical parameters will vary the radiation properties associated with the wavelength. The input impedance has a relation with the pitch angle and conducting wire’s size, as a change in pitch angle values, and the size of the wire will change the input impedance values.

Helical antenna typically shows elliptical polarization, although they can be designed to show circular and linear polarization.

Operational Modes

Helix antennas have the capability to function in many types of operational modes. There are two significant and essential operational modes that we will discuss in detail in the latter part of this article. The two modes are –

• Axial Modes (End- Fire)
• Normal (Broadside)

The three-dimensional figures of both the types of mode of operations are given below.

As we can see in the standard figure, it has a maximum in an imaginary plane which is normal to the axis, and its null is along the axis. The power pattern has a close similarity to the shape of the circular loop.

Now, the maximum is along the helix’s length for the end-fire mode, and the power pattern is similar to the end-fire array. That is why the mode is named as ‘End Fire Mode’.

The axial mode of operation has more preference over the standard mode of operation because it is more realistic or practical, has better efficiency and can show circular polarization with a broader bandwidth. An elliptically polarized antenna can be described as the summation of the two extraneous lined mechanisms in phase-time quadrature.

What does a transmission line do? Explore!

Normal Mode of Helix Antennas

As discussed previously, the antenna’s helical mode has its maximum radiation is directed to a plane normal to the helix axis, and the null radiation is along its axis. The normal mode of operation of helix antenna or broadside mode operation is achievable by comparing the wavelength, that is N L₀ << λ_0.

The helix architecture comes down to a loop of a diameter D as the pitch angle comes to 0 to a lined wire with a length of S while approaching to 90 degrees. Nos, as the helix’s geometry, became a loop and a dipole, the far-field radiation in this mode of operation can be represented respectively by E_ϕ and E_ϴ components of the dipole and the spiral loop.

The helix can be described as N number of small loops and the same number of small dipoles. They are linked with each other in a series manner. The arenas are calculated by using the superposition of the other fields from the rudimentary parts. The loop’s axes and the dipole’s axes coincide with the helix’s axis.

As this model has small dimensions, the current is assumed to be constant. Its operation can be defined by the summation of the fields radiated by a smaller-loops, having a diameter of D and a short dipole having a length of S.

The far-field electric field is given as –

E_ϴ = j * η * k * I₀ * S * e^-jkr Sinϴ / 4πr

The E_ϕ part is given by –

E_ϕ = η* k² * (D/2)² * I₀ * e^-jkr Sinϴ /4r

The ratio of Eϴ and Eϕ gives the axial ratio. The mathematical expression is given below.

AR = | E_ϴ | / | E_ϕ |

Or, AR = 4S / πkD²

Or, AR = 2λS/ (πD)²

The pitch angle is given as – α = tan^-1 (π D/2λ₀)

Axial Mode of operation for Helical Antenna

The axial mode of operation has more preference over the standard mode of operation because it is more realistic or practical, has better efficiency and can show circular polarization with a broader bandwidth.

          This mode is achieved by setting up large S and D. There are some requirements for achieving circular polarization. The range of the circumference of the helix should be in the below-given range.

4/3 > λ₀/C > ¾

The pitch angle also has a limited range. The range of the pitch angle is given below.

12^o ≤ α ≤ 14^o

The terminal impedance range for this mode of operation is between one hundred ohms to two hundred ohms.

The following mathematical operation calculates the gain. For the following equation, S gives the distance between two turns, and N represents the total number of turns in a helical antenna.

G = 15 (C / λ) ² * (NS / λ)

The half-power bandwidth of helical antenna for this mode of operation is given by following mathematical expression.

HPBW = 52 / [ (C/ λ) * √ {(NS / λ)}]

The full null bandwidth of helical antenna for this mode of operation is given by following mathematical expression.

FNBW = 115 λ^3/2 / C * √ (NS)

Check out the radiation pattern of Yagi Uda Antenna!

Helical Antenna Design

• The input impedance is represented as ‘R’. The mathematical equation for ‘R’ is – R = 140 (C / λ₀).
• The half-power bandwidth of helical antenna for this mode of operation is given by following mathematical expression. It has the accuracy of around plus-minus twenty percent. It is a measurement of angle and has a unit in degrees.

HPBW = 52 λ^3/2 / C * √ (NS)

• The full null bandwidth of helical antenna for this mode of operation is given by following mathematical expression. It represents the measure of beamwidth among the Nulls. It has also unit in degrees.

FNBW = 115 λ^3/2 / C * √ (NS)

• D0 represents the directivity of the antenna. The mathematical equation is –

D₀ = 15 * N * C²S / λ₀³

• The following mathematical term gives the Axial Ratio or the AR.

AR = 2N+1 / 2N

• The following expressions give the generalized far-field pattern.

E = sin (π/ 2N) cosϴ sin [ (N/2) * Ψ] / sin (Ψ /2)

Ψ is given by another mathematical equation, and that is further given as Ψ = k₀[S * cos ϴ – (L₀/p)]

                    The value of ‘p’ for general end-fire array is

p = (L₀/ λ₀) * (S/ λ₀ + 1)

                    The value of ‘p’ for Hansen-woodyard end-fire radiation is

                                        p = (L₀/ λ₀) * [S/ λ₀ + {(2N+1)/2N)}]

Helical Antenna Applications

The helical antenna has several applications in modern communication technologies. It has some unique applications because of its design and radiation patterns. Some of the spiral antenna applications are listed below.

• Helical antennas are efficient in radiating very high-frequency range signals.

• Helical antennas are often used for space communications and satellites communications.
• Communications between two planets are possible because of these types of antennas.

Topic of Discussion: MOSFET basics

• What is MOSFET ?
• MOSFET Basics
• Types of MOSFET
• Working principle of MOSFET
• Application of MOSFET
• Different channel effects in MOSFET basics

What is MOSFET?

Definition of MOSFET:

“The Metal-oxide-semiconductor field-effect-transistor (MOSFET), is a form of insulated gate field effect transistor that is made-up by the controllable oxidised silicon based semiconductors”.

Different types of MOS:

• ·        P Channel MOSFET
• ·        N Channel MOSFET

Different types of MOSFET devices:

• ·        Enhancement Mode MOSFET
• ·        Depletion Mode MOSFET

MOSFET Symbol

Working Principle of MOSFET:

MOSFET Basics

A FET is worked as a conductive  semiconductor channel with 2 contacts – the ‘SOURCE ‘ and the DRAIN. The GATE juntion might be comprehended as a  2 -terminal circuitry as a MOS structure working as a rectifing reverse biasing mode. Usually, the GATE  impedance is higher in classic working situations.

The FETs as per these standards are typically MOSFET, JFET,  metal-semiconductor FET (MESFET), and heterostructure FET. Out of these FET, MOSFET is one of the significant one and commonly utilized for various applications.

In a silicon  based MOSFET, the GATE terminal is normally insulated by a specific SiO2 layer. The charge carriers of the conductive channel develop an opposite charge,  e-  in that case, p-type substrate for an n-channel and ‘holes’ for n-type substrate  for the p-channel. This will induced in the semiconductor at the silicon-insulator edge by the applied volt in GATE terminal. The e- will enter and depart the channel at n+ source and drain terminals cotacts for an n-channel metal-oxide-semiconductor field-effect-transistor.  This will be  p+ contacts during the  p-type Metal-oxide-semiconductor field-effect-transistor.

MOSFET layer

Implementation of MOSFET:

Metal-oxide-semiconductor field-effect-transistors are working as discretized circuit and also as an active element. At the present time, these circuits are scaled down into the deep sub micro meter range. At the moment, the standard 0.13-µicro meter standard technology node CMOS is utilized for VLSI technology and, in future 0.1-µicro meter technology will be existing, with a certain upgradation of speed and integration range.

CMOS technology associates with the n-channel and p-channel Metal-oxide-semiconductor field-effect-transistor to consume very less power without constraining the performing speed. New SOI technology accomplish three dimentional integration with multiple layers, with a electrifying increase in integration stupidity. Novel and enriched structures and the combination of Bi-CMOS technology possibly will lead to further enhancements. One of the emerging areas of CMOS is across a variability of applications from audio device of  kHz range to modern wireless application operated at GHz range.

Short channel Effect in MOSFET:

Usually FET sizes are assessed by the device aspect ratio. This is the ratio of the gate length in respect of active vertical measurement of FET. The perpendicular dimension for the oxide breadth is measured as parameter d_i, the source and drain junction depths is considered as parameter r_j.  The source and drain junction depletion depths are diefined by the parameter W_s and W_d respectively. The low aspect ratio is identical with short channel characteristics.

                 L<L_min(µm) = 0.4[r_j(µm)d_i(Å)(W_d + W_s)²(µm²)]^1/3

When L is less than L_min,.

The Metal-oxide-semiconductor field-effect-transistor threshold voltage is consederd as V_T . This voltage will be impacted in a number of ways as a result of gate control. Generally, depletion charges near-source and drain are under the common control. The charge will develop a moderately higher portion of the GATE charge carrier. The depletion charge near drain inflates with increasing drain-source biasing voltage, causing in an additional V_DS-dependent shift in threshold voltage _.

The V_T is a sort of barrier combined with carrier injected from the source to channel direction. This barrier is considerably adjusted by use of a drain biasing voltage. In n-channel Field effect transistors, the drain is dropping the threshold voltage and a concurrent rise in the threshold current with growing VDS.

High Field Effect of MOSFET:

In case of drain-source biasing of a Field effect transistor grow towards the drain saturation voltage which termed as ‘V_SAT’ wherever a range of higher electric field  is created near by  drain. The  velocity of e-  in that region will saturates. In saturation region, the length considered as ∆L of the high-field  increases in the course of the source with growing V_DS, and the performs as if the in effect channel length is decreased  by the parameter ∆L. This phenomenon is entitled as the Channel-length modulation  or  simply termed as CLM in the MOSFET basics. The subsequent simplified manifestation links of V_DS to the length of the saturated region is as follows:

                                             V_DS = V_P + V_α [exp(∆l/l)-1]]

wherever V_p, V_α, and l are parameters interrelated to the e- saturation velocity. Here, V_p is the potential at the point of saturation in the channel, that is commonly estimated by the parameter V_SAT.  Ths agreement is obtained amongst the potential summary which is acquired from the 2D simulation model of an N-channel MOSFET.

Hot Carrier Effects:

Hot-carrier effect is one of  the most important concerns when shrinking FET size into the deep sub micrometre.It decreases the channel length while maintaining high power supply levels. These are increased  to electric field strengths and reasons  of speed up and heating the charged carriers. A comprehensive model for the substrate current is very difficult for circuit-level modelling.

Temperature Dependence and Self-Heating:

The MOSFET basics circuitry is functional in different environs, including different temperatures ranges. Heat created from power dissipation in a circuitry is also significant and the increase in temperature for circuit design is also needed to be considered. The design turns out to be more and more difficult as the device size is becoming very small and power dissipation are increasing with different mode of operation. The thermal characteristics are extensively studied by various models.

For more about MOSFET basics and others electronics related article  click here

CONTENTS

• What is CMOS image sensor ?
• Different types
• Working principle
• Designing
• Architecture

Cover Image By – Zach Dischner, Nerd-Tographer Desk Ornament (9698639550), CC BY 2.0

What is CMOS image sensor ?

CMOS Image and Colour Sensor:

Complementary metal-oxide semiconductor (CMOS) image sensors is comprised of photodiodes with and mixed-signal circuits  ahving capability to amplify small photocurrents into digital signals. The CMOS image sensor is one of the best cricuitry for multiple photography related  applications, i.e digital video cameras, photo scanners, Xerox machine, printing and various others. CMOS are nowadays utilized because of its multiple usage and it’s simple fabrications technique even with constain of sensivity in comparison with CCD.

Three types of the topology of CMOS colour sensors are discussed, namely the transimpedance amplifier (TIA), light to frequency converter, and light integrating.

Working Principle of CMOS Image Sensor:

In general, four types of procedures are available

• Standard CMOS,
• Analog-mixed-signal CMOS,
• Digital CMOS, and
• CMOS image sensor processes.

The most obvious difference between this process and the other processes is the availability of photo devices, such as a pinned photodiode. The advantages of smaller dimension technology are smaller pixel, high spatial resolution, and lower power consumption. A technology lower than 100 nm requires modification to the fabrication process (not following the digital road map) and pixel architecture.

Fundamental parameters such as leakage current (will affect the sensitivity to the light) and operation voltage (will affect dynamic range, i.e., the saturation, a pinned photodiode is most likely not going to work at a low voltage are very important when a process is selected for CIS development. Because of these limitations, a new circuit technique is introduced:

1.  An old circuit, such as a standard pixel circuit cannot be used when using 0.1 micron and lower. This is due to the topology which requires high voltage; because the maximum supply voltage is now lower.

2. Calibration circuit and cancellation circuit are normally employed to reduce noises.

In order to increase the resolution into multi-megapixel and hundreds of frame rate, lower dimension technology is normally chosen. Evidently, it has been reported that 0.13 micron and 0.18 micron are good enough to achieve good imaging performance.

These modifications of the CMOS process have started at 0.25 micron and below to improve their imaging characteristics. As process scaling is going to be much lower than 0.25 micron and below, several fundamental parameters are degraded, namely, photo responsivity and dark current. Therefore, the modifications are focused on mitigating these parameter degradations. System requirements (such as supply voltage and temperature) are also one of the criteria in selecting a suitable process.

The price of tool and development costs will also determine the process selection.

Photo Detetor Devices

The typical photo detector devices are photodiode and phototransistor. Typical photodiode devices are N+/Psub, P+/N_well, N_well/Psub, and P+/N_well/Psub (back-to-back diode) [9]. Phototransistor devices are P+/n_well/Psub (vertical transistor), P+/N_well/P+ (lateral transistor), and N_well/gate (tied phototransistor).

These standard photo devices still require a micro lens and colour filter array. The quantum efficiency of photodiodes in a standard CMOS is usually below 0.3.

The devices which are normally developed for the modified CMOS process are a photogate, pinned photodiode, and amorphous silicon diode. These devices will improve the sensitivity of the CIS. A pinned photodiode, which has a low dark current, offers good imaging characteristics for the CIS.

The photodevices exhibit the parasitic capacitance, which should be considered during the design process. An example of the parasitic capacitance of N_well/Psub is:

                       C_photo = (capacitance per area) × photodevice area.

Design Methodology of CMOS Image Sensors:

The typical design flow of the CMOS image sensor is shown below.

A wave propagation simulation can be done for optics simulation. Commercially available technology computer-aided design tools, such as from Synopsys and Silvaco, can be used to simulate the process or technology of the photodevices. There is a work, (mixed-mode simulation) that combines the technology computer-aided design and pixel-level simulation.

There are many electronic design automation tools available for pixel electrical simulation, these electronic design automation tools are similar to any integrated circuit (IC) design tool, such as spectre, SPICE, Verilog-A, and Verilog. These tools may be time consuming  sometimes if the number of pixels is large.

Indeed, if large pixels together with the deep submicron process are required, more capital has to be provided (cost of tools are more expensive for very deep submicron, especially below 90 nm). Even though the CMOS foundry provides the models for supported design tools, sometimes designers still have to model the sub-block on their own to suit the CIS specification. This can speed up the pixel electrical simulation time, however, this will degrade the accuracy. For system simulation, VHDL-AMS, System-C, or MATLAB can be used to predict the overall function and performance.

CMOS Image Sensor Architecture:

Pixel Level ADC – A digital pixel sensor (DPS) offers a wide dynamic range. The DPS converts the analog values to a digital signa within the pixel range. The processing can also be done at the pixel level.

Chip Level ADC – Chip-level ADC or sometimes matrix-level ADC is depicted in Figure below.

The ADC for this topology has to be very fast, this topology would also consume a very high current. The ADC type suitable for the CIS topology is pipelined ADC. However, successive approximation register (SAR) and flash type ADC have also been reported in the CIS design. The balance of  necessary overall power intake and speed of operation is therefore essential.

Digital Pixel Sensor – The DPS concept is similar to the solution used in the CMOS neuron-stimulus chip. The DPS in number is found useful for on-chip compression. The photodiode is used to discharge the input capacitance of the comparator and photodiode itself. It will be discharged proportionally to the light intensity. When this reaches the threshold, the   comparator’s O/P will be triggered.

Low Power Technique in CMOS Image Sensor:

Biasing method: The subthreshold region or weak inversion biasing is one of the approaches to achieve low current consumption. This technique can be applied to an operational transconductance amplifier (OTA) or an amplifier for an ADC. Triode region biasing can also be used to further reduce power consumption.

Circuit technique: The regenerative latch can be used to reduce the digital power consumption. Reducing/scaling the capacitors in the pipeline stages (for ADC) can also reduce the power consumption.

Advanced power management technique: Another type of biasing or circuit technique, a “smart” approach, such as harvesting solar energy can also be employed to reduce the power consumption. We can also selectively ON only the required readout circuit. Pixels can also be periodically activated to reduce the power consumption further.

Low Noise Techniques in CMOS Image Sensor:

At pixel level: The thermal noise can be reduced by correlated double sampling and oversampling. The flicker noise is reduced by using a large device, periodically biasing the transistor, and proper PMOS substrate voltage biasing.

Column level: The off-chip calibration can be used to reduce fixed pattern noise. The calibration is done to select suitable capacitor weights in the SAR ADC.

ADC level: The kT/C noise is reduced by selecting a suitable value for C_f and C_s of the S/H circuit and buffer.

Photodiode level: The high conversion gain helps to reduce referred-to input noise.

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