- Definitions and Overview of adder
- Types of adder
- Half adder
- Full adder
- BCD adder
Definitions:
An adder is a device which add up two numbers and produce the result. A binary adder is something which deals with addition of binary numbers.
A binary adder is a digital device and needed for digital computations. The operation performed in a binary adder, obeys the rules of binary addition. Here two bits corresponding to 2n are added and the resultant is then added to the carry from the 2n-1 digit.
The binary addition rules are stated as follow. Here 0 is logic low and 1 is logic high. A and B are two inputs.
| A | B | Y = A + B |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 (carry 1) |
Example of addition operations:
- 11111 + 1011 + 101 + 10 + 1
- 11111+ 1011 = 101010
- 101010 + 101 = 101111
- 110001 + 1 = 110010
So the answer is 110010
Types of Adder
This addition operation is implemented by various digital circuitries. They are –
- Half Adder
- Full Adder
- BCD Adder
A binary adder not only performs addition operations but also used in other digital applications. Decoding of address, calculation of index are few of its applications.
Half Adder
A half adder is a type of binary adder which add one bit of data and produces the result. It has two input side through which we supply the digital logic values and it has two outputs through which we receive the result of the operation. The result can be shown in a single digit. The output shows the digit in the sum that has the same significance as the individual digits added. The other output shows the carry bit.
Half Adder Truth table
The operation of the half adder is shown in the following truth table.
| A | B | Sum | Carry | Sum of A & B |
| 0 | 0 | 0 | 0 | 00 |
| 0 | 1 | 1 | 0 | 01 |
| 1 | 0 | 1 | 0 | 01 |
| 1 | 1 | 0 | 1 | 10 |
Now from the truth table, we can observe that the first three rows can represent the sum using a single digit. At the last row, the sum is represented using two digits as it has 1 as carry. Here the sum is zero and carry 1 must be taken to the position of next higher significance.
Sum = A′ B + A B′
Carry = AB
So,
Sum = A XOR B
Carry = A AND B
To implement the logic, we need one XOR gate and one AND gate. XOR gate and AND gate can also be made using universal gates like NAND and NOR. So, a half adder can be designed using only universal gates.
The following image shows A and B as the input and S as the sum and C as the carry.
Full Adder
Another type of binary adder is full adder. It also adds binary data and produces the output. Now, when two binary numbers are added, except the least significant digit there is a carry-in as Ci-1 and carry-out as Ci. The full adder is designed to handle a carry-in for each stage. That is how a full order overcomes the shortcoming of half adder of handling carry-in.
Full adder truth table
| Ai | Bi | Ci-1 | Si | Ci |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Full Adder Circuit
Si = Ai Bi Ci-1 + Ai Bi Ci-1 + Ai Bi Ci-1 + Ai Bi Ci-1 + (Ai Bi + Ai Bi) Ci-1 + (Ai Bi + Ai Bi) Ci-1
And the carry comes as:
Ci = Ai Bi Ci-1 + Ai Bi Ci-1 + Ai Bi Ci-1 + Ai Bi Ci-1
Or, Ci = (Ai Bi + Ai Bi) Ci-1 + (Ai Bi + Ai Bi) Ci-1
Or, Ci = Ai Bi + (Ai Bi + Ai Bi) Ci-1
Now, consider a half adder has inputs A and B. The output sum is S and carry is C. Now the expression of Si and Ci can be obtained from the expressions of Sum and carry of half adder circuit.
Si = S Ci-1 + S Ci-1
Ci = C + S Ci-1
Now, to implement a full adder using half adders we need two half adders and one OR gate. Full adder implementations using half adders is represented in the below figure.
As we can see in the figure that the first half adder (marked as-) has the input Ai and Bi. The second half adder (marked as-) has inputs of C i-1 and output of the first half adder that is S. The output of the second half adder are Si and S Ci-1.
Now, S Ci-1 represents the carry out. The carry of the first half adder that is C and the carry of the second half adder that is S Ci-1 are fed as input of a OR gate. The output of the OR gate is the final carry out of the full adder circuit.
Parallel Binary Adders
A full adder is needed for the addition of bits in each stage of addition except the addition of least significant digits on the other hand two half adders are needed to complete a full adder. It follows the rule that the addition of two n-bit numbers will require 2 * m -1 number of half adder and m-1 numbers of OR gates. This type of binary adders is known as parallel binary adders. The speed of operation of these types of adders are very fast. That is why they are preferred in modern computational devices.
Let us add 101 and 111 as an example of parallel binary adder. The figure shown below represents the addition.
The first half adder (marked as-1) adds the extreme right-hand bits 1 and 1 to produce the binary sum 0 and the carry 1 according to the rules of binary addition. The output of the half adder is fed into the input of the first full adder (marked as- 2). The other two inputs of first full adder are the two next bits that is 0 and 1. The outputs of the first full adder are 0 as sum and 1 as carry. They are further fed into input of second full adder. The other two inputs are 1 and 1. The outputs of the second full adder is 1 as sum and 1 as carry. So, the result of the summation is 1100.
Now, a point to be noted that in place of a half adder at the least significant digit position, a full adder can be used with its carry input made 0.
BCD Adder
The term BCD in BCD adder stand for Binary Coded Decimal. BCD is a special type of binary encoding where each digit has certain number of bits for representation. The BCD of first 10 decimal value is shown in the table.
| Decimal Digit | BCD | |||
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 1 | 1 |
| 4 | 0 | 1 | 0 | 0 |
| 5 | 0 | 1 | 0 | 1 |
| 6 | 0 | 1 | 1 | 0 |
| 7 | 0 | 1 | 1 | 1 |
| 8 | 1 | 0 | 0 | 0 |
| 9 | 1 | 0 | 0 | 1 |
BCD adder has two inputs which varies from 0 to 9. The output varies from 0 to 18 and if the previous carry is considered then the range will be up to 19.
The table for BCD adder is given below.
From the above table, we can observe that from 1 to 9 the binary and the BCD is same. From 10 to 19 decimal numbers, both the binary and codes are different.
The circuit diagram of a BCD adder is shown below.
- In the above diagram there is a four-bit binary adder which has input as addended and augend. It has also input of carry.
- The binary adder gives output of the addition and an carry output.
- Now, using the output and the carry the circuit is further designed to find out the final carry.
- The output is further fed into a 4-bit adder.
- Now, the circuit is designed to make the 1st and 4th bit of the addended number as 0 and also the 2nd and 3rd bit to make as same as Carry. When the carry is 1, the circuit is designed in such a way that the addended will be 0110. 6 is added with augend to get the BCD.
Example of BCD
0110 + 0101 = 1011
Now this is invalid as BCD. The number is greater than 9. So, we have to add 6 to the result.
The final result will be = 1011 + 0110 =
1011 + 0110 = 10001
So the final answer will be 10001
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VHDL implementation of Half adder and Full Adder
HALF-BINARY ADDER DATAFLOW MODELLING
library IEEE ;
use IEEE.std_logic_1164.all ;
entity half_adder_dataflow is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half_adder_dataflow;
architecture Behavioral of half_adder_dataflow is
begin
s <= a XOR b;
c <= a AND b;
end Behavioral;
HALF- BINARY ADDER BEHAVIORAL MODELLING:
entity SUDIPTA_ROY_HALFADD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC;
S : out STD_LOGIC;
Z : out STD_LOGIC);
end SUDIPTA_ROY_HALFADD;
architecture Behavioral of SUDIPTA_ROY_HALFADD is
begin
process(A, B)
begin
if(A=’0′ and B=’0′) then
S <=’0′;
C <=’0′;
elsif(A=’0′ and B=’1′) then
S <=’1′;
C<=’0′;
elsif(A=’1′ and B=’0′) then
S <=’0′;
C<=’1′;
else
S <=’1′;
C<=’1′;
end if;
end process;
end Behavioral;
FULL-ADDER DATAFLOW MODELLING
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SUDIPTA_ROY_FULLADD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Car : out STD_LOGIC);
end SUDIPTA_ROY_FULLADD;
architecture Dataflow of SUDIPTA_ROY_FULLADD is
begin
S<=(A xor B) xor Cin;
Car<=( A and B) or (B and Cin) or (Cin and A);
end Dataflow;
FULL-ADDER BEHAVIORAL MODELLING
entity SAERI_DATT_FULLADD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Car : out STD_LOGIC);
end SAERI_DATT_FULLADD;
architecture Behavioral of SAERI_DATT_FULLADD is
begin
process(A,B,Cin)
begin
if(A=’0′ and B=’0′ and Cin=’0′) then
S<=’0′;
Car<=’0′;
elsif(A=’0′ and B=’0′ and Cin=’1′) then
S<=’1′;
Car<=’0′;
elsif(A=’0′ and B=’1′ and Cin=’0′) then
S<=’1′;
Car<=’0′;
elsif(A=’0′ and B=’1′ and Cin=’1′) then
S<=’0′;
Car<=’1′;
elsif(A=’1′ and B=’0′ and Cin=’0′) then
S<=’1′;
Car<=’0′;
elsif(A=’1′ and B=’0′ and Cin=’1′) then
S<=’0′;
Car<=’1′;
elsif(A=’1′ and B=’1′ and Cin=’0′) then
S<=’0′;
Car<=’1′;
else
S<=’1′;
Car<=’1′;
end if;
end process;
end Behavioral;
Hi, I am Sudipta Roy. I have done B. Tech in Electronics. I am an electronics enthusiast and am currently devoted to the field of Electronics and Communications. I have a keen interest in exploring modern technologies such as AI & Machine Learning. My writings are devoted to providing accurate and updated data to all learners. Helping someone in gaining knowledge gives me immense pleasure.
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