VLSI: Definition,Design,Important Rules And Scaling

A. What is VLSI?

To know about VLSI, we have to know about IC or integrated circuit. An IC is a chip or a processes package which contains transistors or digital circuits in lakhs of number.

VLSI or very large scale integration refers to the process to incorporate transistors (especially MOS transistors) to formulate IC.

VLSI devices consist of thousands of logic gates. They help to create big memory arrays .The arrays are used in microcontroller and microprocessors. It is possible to incorporate 104 to 109 components in a single chip in standard VLSI designing technique.

B. History and background of VLSI

The very first transistor was invented in the year 1947 by J. Barden, W. Shockley, W. Brattain in the Bell Laboratories. All three scientists got noble for the invention in the year 1956. The transistor size got reduced with progress in time and technology.

Jack Kilby and Robert Noyce came up with the idea of IC where components are connected within a single chip. This helped engineers to increase the speed of the operation of various circuits.

Moor’s Law: In the year 1998, Intel Corporation’s co-founder Gordon Moor predicted a trend on the number of components in an integrated circuit.

He predicted that –

“The transistor number inside a microchip gets doubled in every two years”.

The trend is followed with some exceptions.

The progress of integrated circuits leads to the discovery of very large scale integration or VLSI technology. Before the VLSI get invented, there were other technologies as steps. They are discussed below.

• SSI or Small Scale Integration: These type of integrated circuits contains less than ten logic gates. These IC gates have several gates or flip-flops associated with one package.

• MSI or Medium Scale Integration: These packages contain ten to thousand logic gates. MSI ICs can generate basic logic gates. The logic gates can be further used for making sequential and combinational circuits like – mux-demux, encoders-decoders, latch, flip flop, registers, etc.

• LSI or Large Scale Integration: LSI units contain more than one hundred gates. LSI ICs creates more complex circuit structures like – calculators, mini-computers, etc.

• VLSI or Very Large Scale Integration: Contains thousands of logic gates.

• ULSI or Ultra Large Scale Integration: A single chip contains more than 10^9 components.

An overview of transformation is given below.

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C. VLSI Design

A VLSI design has several parts. It needs right and perfect physical, structural, and behavioural representation of the circuit. Redundant and repetitive information is omitted to make a good artwork system. It is achieved by using graphical design description and symbolic representation of components and interconnections.

VLSI architectures use n-channel MOS field-effect transistors and complementary MOS. Complementary MOS or CMOS need both the n-channel and p-channel MOS FETs to be fabricated in the same substrate.

In the 1980s, the demand for increasing package density grew up, and it affected the power consumption of NMOS ICs. The power consumption became so high that the dissipation of the power posed a serious problem. To resolve the issue, the CMOS technology emerged as a solution.

CMOS provides high input impedance, high noise margin, and bidirectional operation. That is why it works smoothly as a switch.

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D. Transistors in VLSI Design

The Metal Oxide Semiconductor Field Effect Transistor or MOSFET is the key component in high-density VLSI chips.

Why is FET used in VLSI?

FET or Field Effect Transistors are probably the simplest forms of the transistor. FETs are used widely in both analogue and digital applications. They are separated by a large value of input resistance and smaller area and size, and they can be used to form circuits with low power consumption. That is why they are widely used in very large scale integration.

CMOS and n-channel MOS are used for their power efficiency.

Characteristics of NMOS Transistors

An NMOS field effect transistor is shown in the above image with the drain current and terminal voltage representations. For an NMOS FET, the source and drain terminals are symmetrical (bidirectional).

When there is no charge on the gate terminal, the drain to source path acts as an open switch. As a thin oxide layer separates the gate from the substrate, it gives a capacitance value. When the gate terminal accumulated enough positive charges, the voltage V_GS exceeds a threshold voltage V_TH. Thus, electrons are attracted in the region under the gate to give a conducting path between the drain and the source.

The gate voltage enhances the channel conductivity by entering into the enhancement mode operation. V_TH ~= 0.2 V_DD gives the VTH.

The majority carrier for this type of FET is holes. When the positive gate to source voltage or V_GS is smaller than V_TH, the majority carrier or holes are repelled into the substrate. Now, on the surface of the p-type there is no carrier. There is no current because of the depletion region.

Now, when the gate to source voltage get higher than the threshold voltage, a healthy amount of minority carriers gets attracted to the surface (Which in our case is the electron). Thus, a channel is formed of inversion layer between the source and drain terminal. 

The below expression gives the drain current ID.

I_D = Charge induced in the channel (Q) / transit time (τ)

The charge transit time τ is the time taken by a charge carrier to cross the channel from the source terminal to drain terminal. For small value of V_DS,

τ = Drain to source distance (L) / Electron drift velocity (v_d) = L / μ E = L² / V_DS μ

E is the electric field and given as, E = V_Ds / L.

μ is the electron mobility. We have said earlier that there is a capacitance value that generates. The capacitance is given as C = εA / D = εWL / D

W is the width, while D is the thickness of the di-oxide layer. ε represents the permittivity of the oxide layer. For silicone di-oxide, the ratio of ε / ε₀ comes as 4. The charge in transit is –

Q = C (V_GS – V_TH – V_DS/2) = (εWL / D) * (V_GS – V_TH – V_DS/2)

The drain current is given as – ID = Q / τ  = (μεW / LD) * (V_GS – V_TH – V_DS/2)V_DS

The resistance will be R = VDS / ID = LD / [ μεW * (V_GS – V_TH – V_DS/2)]

The output characteristics of an NMOS transistor is shown in the below graph.

In the saturation region, the drain current is obtained as –

ID = (μεW / 2LD) (V_GS – V_TH)²

NMOS transistors can also be fabricated with the values of the threshold voltage VTH < = 0. The transistors are referred to as depletion-mode devices.

E. VLSI design rules

VLSI designing has some basic rules. The rules are specifically some geometric specifications simplifying the design of the layout mask. The rules provide details for the minimum dimensions, line layouts and other geometric measures which are obtained from the limits of certain dispensation expertise.

These rules help the designer to design a circuit in the smallest possible area that too without compromising with the performance and reliability.

There are two sets of design rules.

• Rule of Micron – The rule evolves around implementation constrains such as – minimum feature size, smallest allowable feature separations. They are quoted with respect to micro-meter ranges.
• Design rules based on Lambda: the constraints on the distance in the layout are expressed in terms of primary length unit lambda. The rules were developed to simplify the industry-standard micron rules. This allows scaling the capability for different processes. The length unit lambda is the distance by which the geometrical feature of a layer may overlap with that of another layer, and is determined by the limitations of the process technology.

If the length unit is lambda, then all widths, spacings and distances are expressed as m*lambda. M is the scaling factor. The diffused region has a scaling factor of a minimum of 2 lambdas. As per safe thumb rule, diffused regions, which are unconnected, have a separation of 3 lambdas. Metal lines have a minimum width and separation of 3 lambdas in standard VLSI Design.

F. Scaling in VLSI Design

The progress in technology allows us to reduce the size of the devices. This process of size reduction is known as scaling. The main advantages of scaling VLSI Design are that, when the dimensions of an integrated system are scaled to decreased size, the overall performance of the circuit gets improved. Other objectives of scaling are – larger package density, greater execution speed, reduced device cost.

Some of the most used scaling models are –

1. Constant Electric Field Scaling
2. Constant Voltage Scaling.

For the constant electric field, the nonlinear effects are eliminated as the electric field of the circuit remains the same. To understand the scaling in the VLSI Design, we take two parameters as α and β. For constant electric field, β = α and for voltage scaling, β = 1.

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